Searched refs:IMX6UL_CLK_PLL4_AUDIO_DIV (Results 1 – 6 of 6) sorted by relevance
102 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;159 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
194 <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>,197 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
121 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;305 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
101 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
59 #define IMX6UL_CLK_PLL4_AUDIO_DIV 50 macro
219 hws[IMX6UL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", in imx6ul_clocks_init()
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