Searched refs:MMC_TIMING_UHS_SDR104 (Results 1 – 25 of 34) sorted by relevance
12
667 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()736 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()796 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()863 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()1087 zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()1121 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
254 } else if (timing == MMC_TIMING_UHS_SDR104) { in dw_mci_exynos_config_hs400()315 case MMC_TIMING_UHS_SDR104: in dw_mci_exynos_set_ios()
98 { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },341 case MMC_TIMING_UHS_SDR104: in sdhci_sprd_set_uhs_signaling()
1015 case MMC_TIMING_UHS_SDR104: in sd_set_timing()1102 case MMC_TIMING_UHS_SDR104: in sdmmc_set_ios()1321 case MMC_TIMING_UHS_SDR104: in sdmmc_execute_tuning()1341 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || in sdmmc_execute_tuning()
313 (host->timing != MMC_TIMING_UHS_SDR104)) in sdhci_o2_execute_tuning()536 if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) { in sdhci_pci_o2_set_clock()
114 case MMC_TIMING_UHS_SDR104: in dw_mci_rk3288_set_ios()
79 (timing == MMC_TIMING_UHS_SDR104)) in sdhci_brcmstb_set_uhs_signaling()
278 case MMC_TIMING_UHS_SDR104: in arasan_select_phy_clock()
411 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9750_set_clock()557 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9755_set_clock()
237 case MMC_TIMING_UHS_SDR104: in dw_mci_hs_set_timing()
254 host->timing != MMC_TIMING_UHS_SDR104) in sdhci_cdns_execute_tuning()
285 case MMC_TIMING_UHS_SDR104: in sdhci_st_set_uhs_signaling()
140 (timing == MMC_TIMING_UHS_SDR104)) in dwcmshc_set_uhs_signaling()
248 if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) { in mmci_sdmmc_set_clkreg()
264 case MMC_TIMING_UHS_SDR104: in pxav3_set_uhs_signaling()
47 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000,53 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000,
206 else if (timing == MMC_TIMING_UHS_SDR104) in xenon_set_uhs_signaling()
1052 case MMC_TIMING_UHS_SDR104: in sd_set_timing()1121 case MMC_TIMING_UHS_SDR104: in sdmmc_set_ios()
531 case MMC_TIMING_UHS_SDR104: in tegra_sdhci_pad_autocalib()1008 case MMC_TIMING_UHS_SDR104: in tegra_sdhci_set_uhs_signaling()
751 case MMC_TIMING_UHS_SDR104: in xenon_hs_delay_adj()
138 case MMC_TIMING_UHS_SDR104: in mmc_ios_show()
521 timing = MMC_TIMING_UHS_SDR104; in sdio_set_bus_speed_mode()602 (card->host->ios.timing == MMC_TIMING_UHS_SDR104))) in mmc_sdio_init_uhs_card()
255 &map->phase[MMC_TIMING_UHS_SDR104]); in mmc_of_parse_clk_phase()
485 timing = MMC_TIMING_UHS_SDR104; in sd_set_bus_speed_mode()662 card->host->ios.timing == MMC_TIMING_UHS_SDR104)) { in mmc_sd_init_uhs_card()
59 #define MMC_TIMING_UHS_SDR104 6 macro
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