| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | dimgrey_cavefish_reg_init.c | 37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
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| A D | aldebaran_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in aldebaran_reg_base_init()
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| A D | arct_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in arct_reg_base_init()
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| A D | vega10_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
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| A D | vega20_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
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| /linux/drivers/gpu/drm/amd/include/ |
| A D | cyan_skillfish_ip_offset.h | 81 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0 } }, variable
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| A D | navi10_ip_offset.h | 79 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } }, variable
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| A D | navi12_ip_offset.h | 109 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, variable
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| A D | vega20_ip_offset.h | 81 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } }, variable
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| A D | dimgrey_cavefish_ip_offset.h | 102 static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } }, variable
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| A D | navi14_ip_offset.h | 109 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, variable
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| A D | sienna_cichlid_ip_offset.h | 109 static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, variable
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| A D | beige_goby_ip_offset.h | 117 static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } }, variable
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| A D | vega10_ip_offset.h | 148 static const struct IP_BASE __maybe_unused MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } }, variable
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| A D | renoir_ip_offset.h | 144 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, variable
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| A D | yellow_carp_offset.h | 104 static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } }, variable
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| A D | vangogh_ip_offset.h | 130 static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } }, variable
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| A D | arct_ip_offset.h | 87 static const struct IP_BASE MMHUB_BASE ={ { { { 0x00012440, 0x0001A000, 0x00408800, 0, 0… variable
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| A D | aldebaran_ip_offset.h | 126 static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } }, variable
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| /linux/drivers/gpu/drm/amd/display/dc/dce120/ |
| A D | dce120_resource.c | 150 #define MMHUB_BASE(seg) \ macro
154 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_resource.c | 293 #define MMHUB_BASE(seg) \ macro
297 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_resource.c | 208 #define MMHUB_BASE(seg) \ macro
212 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
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| /linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| A D | dcn301_resource.c | 170 #define MMHUB_BASE(seg) \ macro
174 .reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \
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| /linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_resource.c | 365 #define MMHUB_BASE(seg) \ macro
369 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
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| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_resource.c | 322 #define MMHUB_BASE(seg) \ macro
326 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
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