Searched refs:MP0_HWIP (Results 1 – 11 of 11) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_discovery.c | 165 [MP0_HWIP] = MP0_HWID,
701 switch (adev->ip_versions[MP0_HWIP][0]) { in amdgpu_discovery_set_psp_ip_blocks()
736 adev->ip_versions[MP0_HWIP][0]); in amdgpu_discovery_set_psp_ip_blocks()
1011 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
1032 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
1054 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); in amdgpu_discovery_set_ip_blocks()
1070 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); in amdgpu_discovery_set_ip_blocks()
1091 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); in amdgpu_discovery_set_ip_blocks()
1120 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); in amdgpu_discovery_set_ip_blocks()
1144 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); in amdgpu_discovery_set_ip_blocks()
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| A D | amdgpu_psp.c | 78 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_check_pmfw_centralized_cstate_management()
101 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_early_init()
283 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2)) { in psp_sw_init()
326 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || in psp_sw_init()
327 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { in psp_sw_init()
357 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || in psp_sw_fini()
358 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) in psp_sw_fini()
617 switch (psp->adev->ip_versions[MP0_HWIP][0]) { in psp_skip_tmr()
1014 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || in psp_xgmi_terminate()
1015 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && in psp_xgmi_terminate()
[all …]
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| A D | psp_v13_0.c | 50 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_v13_0_init_microcode()
61 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_v13_0_init_microcode()
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| A D | dimgrey_cavefish_reg_init.c | 40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
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| A D | aldebaran_reg_init.c | 39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in aldebaran_reg_base_init()
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| A D | arct_reg_init.c | 39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in arct_reg_base_init()
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| A D | vega10_reg_init.c | 39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega10_reg_base_init()
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| A D | vega20_reg_init.c | 39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega20_reg_base_init()
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| A D | psp_v11_0.c | 96 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_v11_0_init_microcode()
132 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_v11_0_init_microcode()
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| A D | amdgpu.h | 743 MP0_HWIP, enumerator
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| A D | soc15.c | 1464 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) { in soc15_common_get_clockgating_state()
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Completed in 28 milliseconds