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Searched refs:MP1_HWIP (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dsmu_v11_0.c93 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) || in smu_v11_0_init_microcode()
94 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)))) in smu_v11_0_init_microcode()
97 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v11_0_init_microcode()
124 adev->ip_versions[MP1_HWIP][0]); in smu_v11_0_init_microcode()
242 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v11_0_check_fw_version()
275 adev->ip_versions[MP1_HWIP][0]); in smu_v11_0_check_fw_version()
756 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11) || in smu_v11_0_init_display_count()
757 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) || in smu_v11_0_init_display_count()
759 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) in smu_v11_0_init_display_count()
1150 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v11_0_gfx_off_control()
[all …]
A Dnavi10_ppt.c348 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && in navi10_get_allowed_feature_mask()
357 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && in navi10_get_allowed_feature_mask()
928 switch (adev->ip_versions[MP1_HWIP][0]) { in navi1x_get_smu_metrics_data()
938 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) || in navi1x_get_smu_metrics_data()
1515 switch (adev->ip_versions[MP1_HWIP][0]) { in navi10_populate_umd_state_clk()
2568 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0) || in navi10_need_umc_cdr_workaround()
2569 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) in navi10_need_umc_cdr_workaround()
2697 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) in navi10_run_umc_cdr_workaround()
2703 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) in navi10_run_umc_cdr_workaround()
3157 switch (adev->ip_versions[MP1_HWIP][0]) { in navi1x_get_gpu_metrics()
[all …]
A Dsienna_cichlid_ppt.c77 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
85 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) in get_table_size()
301 (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) && in sienna_cichlid_get_allowed_feature_mask()
499 if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && in sienna_cichlid_get_throttler_status_locked()
520 bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && in sienna_cichlid_get_smu_metrics_data()
1126 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && in sienna_cichlid_print_clk_levels()
1893 if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && in sienna_cichlid_dump_od_table()
2117 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && in sienna_cichlid_od_edit_dpm_table()
2821 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) { in sienna_cichlid_dump_pptable()
3581 bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && in sienna_cichlid_get_gpu_metrics()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_discovery.c166 [MP1_HWIP] = MP1_HWID,
744 switch (adev->ip_versions[MP1_HWIP][0]) { in amdgpu_discovery_set_smu_ip_blocks()
777 adev->ip_versions[MP1_HWIP][0]); in amdgpu_discovery_set_smu_ip_blocks()
1012 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
1033 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
1055 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); in amdgpu_discovery_set_ip_blocks()
1071 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); in amdgpu_discovery_set_ip_blocks()
1092 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); in amdgpu_discovery_set_ip_blocks()
1121 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); in amdgpu_discovery_set_ip_blocks()
1145 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); in amdgpu_discovery_set_ip_blocks()
A Dsoc15.c344 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) || in soc15_get_xclk()
345 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1)) in soc15_get_xclk()
347 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) || in soc15_get_xclk()
348 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1)) in soc15_get_xclk()
579 switch (adev->ip_versions[MP1_HWIP][0]) { in soc15_asic_reset_method()
644 switch (adev->ip_versions[MP1_HWIP][0]) { in soc15_supports_baco()
A Ddimgrey_cavefish_reg_init.c41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
A Daldebaran_reg_init.c40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in aldebaran_reg_base_init()
A Darct_reg_init.c40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in arct_reg_base_init()
A Dvega10_reg_init.c40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
A Dvega20_reg_init.c40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
A Dnv.c514 switch (adev->ip_versions[MP1_HWIP][0]) { in nv_asic_reset_method()
A Damdgpu.h744 MP1_HWIP, enumerator
/linux/drivers/gpu/drm/amd/pm/swsmu/
A Damdgpu_smu.c462 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) in is_support_sw_smu()
582 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_set_funcs()
703 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || in smu_late_init()
704 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) in smu_late_init()
1150 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_smc_hw_setup()
1301 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { in smu_start_smc_engine()
1426 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_disable_dpms()
1448 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_disable_dpms()
2311 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_get_power_limit()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0.c92 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v13_0_init_microcode()
98 adev->ip_versions[MP1_HWIP][0]); in smu_v13_0_init_microcode()
217 switch (smu->adev->ip_versions[MP1_HWIP][0]) { in smu_v13_0_check_fw_version()
227 smu->adev->ip_versions[MP1_HWIP][0]); in smu_v13_0_check_fw_version()
749 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v13_0_gfx_off_control()

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