Home
last modified time | relevance | path

Searched refs:MUX_GATE (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/clk/mediatek/
A Dclk-mt2712.c742 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
745 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",
747 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel",
749 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel",
751 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel",
758 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",
785 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel",
787 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel",
875 MUX_GATE(CLK_TOP_DI_SEL, "di_sel",
877 MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel",
[all …]
A Dclk-mt2701.c494 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
497 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
499 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
501 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,
508 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,
526 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
533 MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
549 MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents,
551 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents,
579 MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents,
[all …]
A Dclk-mt7629.c487 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
489 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
493 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
496 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
505 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
507 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
509 MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
529 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
532 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
534 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", hif_parents,
[all …]
A Dclk-mt8135.c352 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
354 MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),
355 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
358 MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),
359 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
361 MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),
372 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
375 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
379 MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7),
381 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
[all …]
A Dclk-mt7622.c515 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
517 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
521 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
525 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
535 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
537 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
539 MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
565 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
567 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
571 MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
[all …]
A Dclk-mt8173.c545 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
547 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
548 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
550 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31),
553 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
554 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
568 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15),
569 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
577 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
587 MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),
[all …]
A Dclk-mt6797.c334 MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
338 MUX_GATE(CLK_TOP_MUX_CAMTG, "camtg_sel", camtg, 0x0060, 0, 2, 7),
343 MUX_GATE(CLK_TOP_MUX_USB20, "usb20_sel", usb20_parents,
347 MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents,
349 MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents,
351 MUX_GATE(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", msdc30_2_parents,
353 MUX_GATE(CLK_TOP_MUX_AUDIO, "audio_sel", audio_parents,
365 MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents,
367 MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents,
375 MUX_GATE(CLK_TOP_MUX_AUDIO_H, "audio_h_sel", audio_h_parents,
[all …]
A Dclk-mtk.h111 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ macro

Completed in 21 milliseconds