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Searched refs:MUX_GATE_CLR_SET_UPD (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/clk/mediatek/
A Dclk-mt8195-topckgen.c870 MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
874 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
876 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
879 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
881 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
885 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
921 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
948 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
952 MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",
955 MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",
[all …]
A Dclk-mt6779.c643 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
672 MUX_GATE_CLR_SET_UPD(CLK_TOP_F52M_MFG, "f52m_mfg_sel",
692 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel",
696 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel",
718 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disppwm_sel",
721 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "usb_top_sel",
735 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "seninf1_sel",
738 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "seninf2_sel",
744 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG1, "aud_eng1_sel",
747 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG2, "aud_eng2_sel",
[all …]
A Dclk-mt8192.c714 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel",
722 MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel",
729 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel",
731 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel",
733 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel",
735 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel",
760 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel",
778 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel",
781 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL, "dpi_sel",
792 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel",
[all …]
A Dclk-mt8183.c528 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
531 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
534 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
538 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel",
541 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel",
544 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel",
551 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel",
573 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel",
603 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel",
626 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel",
[all …]
A Dclk-mt6765.c386 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
393 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
399 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
406 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",
409 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
412 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
419 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
425 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
428 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
438 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel",
[all …]
A Dclk-mux.h70 #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ macro

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