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/linux/Documentation/devicetree/bindings/interrupt-controller/
A Dopen-pic.txt1 * Open PIC Binding
4 representation of an Open PIC compliant interrupt controller. This binding is
5 based on the binding defined for Open PIC in [1] and is a superset of that
13 - compatible: Specifies the compatibility list for the PIC. The type
20 as an Open PIC. No property value shall be defined.
31 - pic-no-reset: The presence of this property indicates that the PIC
55 * An Open PIC interrupt controller
62 // this Open PIC node do not need a parent address specifier.
71 // Compatible with Open PIC.
74 // The PIC shall not be reset.
[all …]
A Dmarvell,armada-8k-pic.txt1 Marvell Armada 7K/8K PIC Interrupt controller
4 This is the Device Tree binding for the PIC, a secondary interrupt
13 - reg: the register area for the PIC interrupt controller
A Dloongson,pch-pic.yaml7 title: Loongson PCH PIC Controller
27 to PCH PIC.
A Dcdns,xtensa-mx.txt6 Remaining properties have exact same meaning as in Xtensa PIC
A Dgoogle,goldfish-pic.txt1 Android Goldfish PIC
A Dloongson,htpic.yaml17 interrupts from PCH PIC connected on HyperTransport bus.
A Dcdns,xtensa-pic.txt1 * Xtensa built-in Programmable Interrupt Controller (PIC)
/linux/arch/powerpc/boot/dts/
A Dmpc8272ads.dts74 interrupt-parent = <&PIC>;
108 interrupt-parent = <&PIC>;
156 interrupt-parent = <&PIC>;
167 interrupt-parent = <&PIC>;
176 interrupt-parent = <&PIC>;
191 interrupt-parent = <&PIC>;
197 interrupt-parent = <&PIC>;
210 interrupt-parent = <&PIC>;
223 interrupt-parent = <&PIC>;
234 interrupt-parent = <&PIC>;
[all …]
A Dpq2fads.dts73 interrupt-parent = <&PIC>;
106 interrupt-parent = <&PIC>;
155 interrupt-parent = <&PIC>;
166 interrupt-parent = <&PIC>;
177 interrupt-parent = <&PIC>;
189 interrupt-parent = <&PIC>;
207 interrupt-parent = <&PIC>;
213 interrupt-parent = <&PIC>;
225 interrupt-parent = <&PIC>;
231 PIC: interrupt-controller@10c00 { label
A Dep8248e.dts72 interrupt-parent = <&PIC>;
77 interrupt-parent = <&PIC>;
135 interrupt-parent = <&PIC>;
148 interrupt-parent = <&PIC>;
161 interrupt-parent = <&PIC>;
174 interrupt-parent = <&PIC>;
186 interrupt-parent = <&PIC>;
192 PIC: interrupt-controller@10c00 { label
A Dmgcoge.dts140 interrupt-parent = <&PIC>;
153 interrupt-parent = <&PIC>;
164 interrupt-parent = <&PIC>;
194 interrupt-parent = <&PIC>;
207 interrupt-parent = <&PIC>;
218 interrupt-parent = <&PIC>;
226 interrupt-parent = <&PIC>;
253 PIC: interrupt-controller@10c00 { label
A Dmpc885ads.dts32 interrupt-parent = <&PIC>;
103 interrupt-parent = <&PIC>;
115 interrupt-parent = <&PIC>;
120 PIC: interrupt-controller@0 { label
134 interrupt-parent = <&PIC>;
171 interrupt-parent = <&PIC>;
228 interrupt-parent = <&PIC>;
A Dtqm8xx.dts39 interrupt-parent = <&PIC>;
73 interrupt-parent = <&PIC>;
85 interrupt-parent = <&PIC>;
115 interrupt-parent = <&PIC>;
120 PIC: pic@0 { label
161 interrupt-parent = <&PIC>;
A Dep88xc.dts32 interrupt-parent = <&PIC>;
98 interrupt-parent = <&PIC>;
110 interrupt-parent = <&PIC>;
115 PIC: interrupt-controller@0 { label
129 interrupt-parent = <&PIC>;
165 interrupt-parent = <&PIC>;
A Dadder875-redboot.dts37 interrupt-parent = <&PIC>;
100 interrupt-parent = <&PIC>;
112 interrupt-parent = <&PIC>;
117 PIC: interrupt-controller@0 { label
156 interrupt-parent = <&PIC>;
A Dadder875-uboot.dts37 interrupt-parent = <&PIC>;
99 interrupt-parent = <&PIC>;
111 interrupt-parent = <&PIC>;
116 PIC: interrupt-controller@0 { label
155 interrupt-parent = <&PIC>;
A Dmpc866ads.dts32 interrupt-parent = <&PIC>;
83 interrupt-parent = <&PIC>;
88 PIC: pic@0 { label
129 interrupt-parent = <&PIC>;
A Dgamecube.dts50 interrupt-parent = <&PIC>;
62 PIC: pic { label
/linux/Documentation/x86/i386/
A DIO-APIC.rst30 2: 0 XT-PIC cascade
31 13: 1 XT-PIC fpu
39 Some interrupts are still listed as 'XT PIC', but this is not a problem;
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/
A Dusb.txt13 interrupt-parent = <&PIC>;
/linux/Documentation/devicetree/bindings/usb/
A Dmaxim,max3421.txt21 interrupt-parent = <&PIC>;
/linux/arch/openrisc/boot/dts/
A Dor1ksim.dts34 * OR1K PIC is built into CPU and accessed via special purpose
A Dsimple_smp.dts46 * OR1K PIC is built into CPU and accessed via special purpose
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
A Dserial.txt27 interrupt-parent = <&PIC>;
/linux/Documentation/devicetree/bindings/mmc/
A Dmmc-spi-slot.txt28 interrupt-parent = <&PIC>;

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