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Searched refs:PORT_BASE (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/scsi/hisi_sas/
A Dhisi_sas_v1_hw.c112 #define PORT_BASE (0x800) macro
114 #define PHY_CFG (PORT_BASE + 0x0)
126 #define PHY_CTRL (PORT_BASE + 0x14)
130 #define PHY_PCN (PORT_BASE + 0x44)
131 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
132 #define SL_CONTROL (PORT_BASE + 0x94)
135 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
136 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
157 #define CHL_INT0 (PORT_BASE + 0x1b0)
172 #define CHL_INT1 (PORT_BASE + 0x1b4)
[all …]
A Dhisi_sas_v2_hw.c170 #define PORT_BASE (0x2000) macro
172 #define PHY_CFG (PORT_BASE + 0x0)
181 #define PHY_CTRL (PORT_BASE + 0x14)
185 #define SL_CFG (PORT_BASE + 0x84)
186 #define PHY_PCN (PORT_BASE + 0x44)
187 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
188 #define SL_CONTROL (PORT_BASE + 0x94)
203 #define TXID_AUTO (PORT_BASE + 0xb8)
223 #define CHL_INT0 (PORT_BASE + 0x1b4)
234 #define CHL_INT1 (PORT_BASE + 0x1b8)
[all …]
A Dhisi_sas_v3_hw.c185 #define PORT_BASE (0x2000) macro
186 #define PHY_CFG (PORT_BASE + 0x0)
199 #define PHY_CTRL (PORT_BASE + 0x14)
204 #define SERDES_CFG (PORT_BASE + 0x1c)
221 #define SL_CFG (PORT_BASE + 0x84)
222 #define AIP_LIMIT (PORT_BASE + 0x90)
223 #define SL_CONTROL (PORT_BASE + 0x94)
251 #define CHL_INT0 (PORT_BASE + 0x1b4)
262 #define CHL_INT1 (PORT_BASE + 0x1b8)
275 #define CHL_INT2 (PORT_BASE + 0x1bc)
[all …]
/linux/tools/testing/selftests/net/
A Dpsock_fanout.c416 typeflags, (uint16_t)PORT_BASE, in test_datapath()
417 (uint16_t)(PORT_BASE + port_off)); in test_datapath()
432 pair_udp_open(fds_udp[0], PORT_BASE); in test_datapath()
433 pair_udp_open(fds_udp[1], PORT_BASE + port_off); in test_datapath()
A Dpsock_lib.h21 #define PORT_BASE 8000 macro
A Dpsock_tpacket.c229 pair_udp_open(udp_sock, PORT_BASE); in walk_v1_v2_rx()
590 pair_udp_open(udp_sock, PORT_BASE); in walk_v3_rx()
/linux/drivers/ata/
A Dahci_ceva.c70 #define PORT_BASE 0x100 macro
185 writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); in ahci_ceva_setup()
/linux/drivers/net/ethernet/chelsio/cxgb4/
A Dt4_regs.h58 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) macro
59 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))

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