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Searched refs:QE_PIO_PINS (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/soc/fsl/qe/
A Dqe_io.c64 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? in __par_io_config_pin()
69 pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS - in __par_io_config_pin()
70 (pin % (QE_PIO_PINS / 2) + 1) * 2)); in __par_io_config_pin()
73 new_mask2bits = (u32) (dir << (QE_PIO_PINS - in __par_io_config_pin()
74 (pin % (QE_PIO_PINS / 2) + 1) * 2)); in __par_io_config_pin()
77 if (pin > (QE_PIO_PINS / 2) - 1) { in __par_io_config_pin()
87 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? in __par_io_config_pin()
92 (pin % (QE_PIO_PINS / 2) + 1) * 2)); in __par_io_config_pin()
94 if (pin > (QE_PIO_PINS / 2) - 1) { in __par_io_config_pin()
124 if (pin >= QE_PIO_PINS) in par_io_data_set()
[all …]
A Dgpio.c28 unsigned long pin_flags[QE_PIO_PINS];
57 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); in qe_gpio_get()
68 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); in qe_gpio_set()
98 qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i)); in qe_gpio_set_multiple()
100 qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i)); in qe_gpio_set_multiple()
248 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); in qe_pin_set_dedicated()
249 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); in qe_pin_set_dedicated()
250 bool second_reg = pin > (QE_PIO_PINS / 2) - 1; in qe_pin_set_dedicated()
323 gc->ngpio = QE_PIO_PINS; in qe_add_gpiochips()
/linux/include/soc/fsl/qe/
A Dqe.h139 #define QE_PIO_PINS 32 macro

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