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Searched refs:REG_UPDATE (Results 1 – 25 of 85) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_mmhubbub.c141 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1); in mmhubbub2_config_mcif_buf()
164 REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x0); in mmhubbub2_config_mcif_arb()
167 REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x1); in mmhubbub2_config_mcif_arb()
170 REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x2); in mmhubbub2_config_mcif_arb()
173 REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x3); in mmhubbub2_config_mcif_arb()
180 REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, in mmhubbub2_config_mcif_arb()
184 REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, in mmhubbub2_config_mcif_arb()
188 REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, in mmhubbub2_config_mcif_arb()
192 REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, in mmhubbub2_config_mcif_arb()
226 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 1); in mmhubbub2_enable_mcif()
[all …]
A Ddcn20_dwb.c83 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 1); in dwb2_config_dwb_cnv()
89 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 0); in dwb2_config_dwb_cnv()
118 REG_UPDATE(WB_ENABLE, WB_ENABLE, 1); in dwb2_enable()
130 REG_UPDATE(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, 0); in dwb2_enable()
144 REG_UPDATE(WB_ENABLE, WB_ENABLE, 0); in dwb2_disable()
147 REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1); in dwb2_disable()
148 REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0); in dwb2_disable()
181 REG_UPDATE(CNV_UPDATE, CNV_UPDATE_LOCK, 1); in dwb2_update()
192 REG_UPDATE(CNV_UPDATE, CNV_UPDATE_LOCK, 0); in dwb2_update()
222 REG_UPDATE(CNV_MODE, CNV_EYE_SELECTION, 0); in dwb2_set_stereo()
[all …]
A Ddcn20_dpp.c83 REG_UPDATE(OBUF_MEM_PWR_CTRL, in dpp2_power_on_obuf()
86 REG_UPDATE(DSCL_MEM_PWR_CTRL, in dpp2_power_on_obuf()
122 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp2_cnv_setup()
123 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp2_cnv_setup()
124 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp2_cnv_setup()
125 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp2_cnv_setup()
224 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp2_cnv_setup()
244 REG_UPDATE(CURSOR_CONTROL, in dpp2_cnv_setup()
246 REG_UPDATE(CURSOR0_CONTROL, in dpp2_cnv_setup()
370 REG_UPDATE(CURSOR0_COLOR0, in dpp2_set_cursor_attributes()
[all …]
A Ddcn20_stream_encoder.c85 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc2_update_hdmi_info_packet()
92 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc2_update_hdmi_info_packet()
99 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc2_update_hdmi_info_packet()
106 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc2_update_hdmi_info_packet()
324 REG_UPDATE(DP_SEC_CNTL6, in enc2_dp_set_dsc_pps_info_packet()
404 REG_UPDATE(DIG_FE_CNTL, in enc2_set_dynamic_metadata()
408 REG_UPDATE(DME_CONTROL, in enc2_set_dynamic_metadata()
411 REG_UPDATE(DME_CONTROL, in enc2_set_dynamic_metadata()
420 REG_UPDATE(DIG_FE_CNTL, in enc2_set_dynamic_metadata()
503 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); in enc2_stream_encoder_dp_unblank()
[all …]
A Ddcn20_optc.c55 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, in optc2_enable_crtc()
59 REG_UPDATE(CONTROL, in optc2_enable_crtc()
119 REG_UPDATE(OTG_GSL_CONTROL, in optc2_use_gsl_as_master_update_lock()
189 REG_UPDATE(OPTC_WIDTH_CONTROL, in optc2_set_dsc_config()
212 REG_UPDATE(OTG_H_TIMING_CNTL, in optc2_set_odm_bypass()
253 REG_UPDATE(OPTC_WIDTH_CONTROL, in optc2_set_odm_combine()
289 REG_UPDATE(DWB_SOURCE_SELECT, in optc2_set_dwb_source()
292 REG_UPDATE(DWB_SOURCE_SELECT, in optc2_set_dwb_source()
353 REG_UPDATE(OTG_GLOBAL_CONTROL1, in optc2_align_vblanks()
374 REG_UPDATE(OTG_CONTROL, in optc2_align_vblanks()
[all …]
A Ddcn20_dwb_scl.c751 REG_UPDATE(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, h_ratio_luma); in dwb_program_horz_scalar()
754 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, h_taps_luma - 1); in dwb_program_horz_scalar()
755 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, h_taps_chroma - 1); in dwb_program_horz_scalar()
777 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, h_init_phase_luma_int); in dwb_program_horz_scalar()
778 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, h_init_phase_luma_frac); in dwb_program_horz_scalar()
779 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, h_init_phase_chroma_int); in dwb_program_horz_scalar()
829 REG_UPDATE(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, v_ratio_luma); in dwb_program_vert_scalar()
832 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, v_taps_luma - 1); in dwb_program_vert_scalar()
833 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, v_taps_chroma - 1); in dwb_program_vert_scalar()
856 REG_UPDATE(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, v_init_phase_luma_int); in dwb_program_vert_scalar()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_mmhubbub.c100 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false); in mmhubbub3_warmup_mcif()
149 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1); in mmhubbub3_config_mcif_buf()
167 REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x0); in mmhubbub3_config_mcif_arb()
170 REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x1); in mmhubbub3_config_mcif_arb()
173 REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x2); in mmhubbub3_config_mcif_arb()
176 REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x3); in mmhubbub3_config_mcif_arb()
183 REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, in mmhubbub3_config_mcif_arb()
187 REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, in mmhubbub3_config_mcif_arb()
191 REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, in mmhubbub3_config_mcif_arb()
195 REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, in mmhubbub3_config_mcif_arb()
[all …]
A Ddcn30_vpg.c178 REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL, in vpg3_update_generic_info_packet()
182 REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL, in vpg3_update_generic_info_packet()
186 REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL, in vpg3_update_generic_info_packet()
190 REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL, in vpg3_update_generic_info_packet()
194 REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL, in vpg3_update_generic_info_packet()
198 REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL, in vpg3_update_generic_info_packet()
202 REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL, in vpg3_update_generic_info_packet()
206 REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL, in vpg3_update_generic_info_packet()
210 REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL, in vpg3_update_generic_info_packet()
214 REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL, in vpg3_update_generic_info_packet()
[all …]
A Ddcn30_dio_stream_encoder.c104 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc3_update_hdmi_info_packet()
111 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc3_update_hdmi_info_packet()
118 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc3_update_hdmi_info_packet()
125 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc3_update_hdmi_info_packet()
132 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc3_update_hdmi_info_packet()
139 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc3_update_hdmi_info_packet()
146 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, in enc3_update_hdmi_info_packet()
377 REG_UPDATE(DP_GSP11_CNTL, in enc3_dp_set_dsc_pps_info_packet()
390 REG_UPDATE(DP_GSP11_CNTL, in enc3_dp_set_dsc_pps_info_packet()
392 REG_UPDATE(DP_SEC_CNTL, in enc3_dp_set_dsc_pps_info_packet()
[all …]
A Ddcn30_dwb.c76 REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 1); in dwb3_config_fc()
82 REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 0); in dwb3_config_fc()
86 REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_RATE, params->capture_rate); in dwb3_config_fc()
97 REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, 1); in dwb3_enable()
111 REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE); in dwb3_enable()
114 REG_UPDATE(FC_FLOW_CTRL, FC_FIRST_PIXEL_DELAY_COUNT, 96); in dwb3_enable()
127 REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, 0); in dwb3_disable()
149 REG_UPDATE(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, 1); in dwb3_update()
165 REG_UPDATE(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, 0); in dwb3_update()
193 REG_UPDATE(FC_MODE_CTRL, FC_EYE_SELECTION, 0); in dwb3_set_stereo()
[all …]
A Ddcn30_afmt.c56 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); in afmt3_setup_hdmi_audio()
71 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); in afmt3_setup_hdmi_audio()
141 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); in afmt3_se_audio_setup()
145 REG_UPDATE(AFMT_MEM_PWR, AFMT_MEM_PWR_FORCE, 0); in afmt3_se_audio_setup()
158 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); in afmt3_audio_mute_control()
167 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); in afmt3_audio_info_immediate_update()
179 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); in afmt3_setup_dp_audio()
188 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); in afmt3_setup_dp_audio()
191 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); in afmt3_setup_dp_audio()
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_stream_encoder.c102 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, in dce110_update_generic_info_packet()
143 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
147 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
151 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
155 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
159 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
163 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
167 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
171 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
661 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); in dce110_stream_encoder_hdmi_set_stream_attribute()
[all …]
A Ddce_dmcu.c200 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
204 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
208 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
212 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
229 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
276 REG_UPDATE(MASTER_COMM_CMD_REG, in dce_dmcu_setup_psr()
635 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dcn10_dmcu_setup_psr()
639 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dcn10_dmcu_setup_psr()
643 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dcn10_dmcu_setup_psr()
647 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dcn10_dmcu_setup_psr()
[all …]
A Ddce_ipp.c51 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); in dce_ipp_cursor_set_position()
55 REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable); in dce_ipp_cursor_set_position()
66 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); in dce_ipp_cursor_set_position()
77 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); in dce_ipp_cursor_set_attributes()
136 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); in dce_ipp_cursor_set_attributes()
146 REG_UPDATE(PRESCALE_GRPH_CONTROL, in dce_ipp_program_prescale()
162 REG_UPDATE(PRESCALE_GRPH_CONTROL, in dce_ipp_program_prescale()
166 REG_UPDATE(INPUT_GAMMA_CONTROL, in dce_ipp_program_prescale()
186 REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0); in dce_ipp_program_input_lut()
215 REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); in dce_ipp_program_input_lut()
[all …]
A Ddce_mem_input.c169 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_urgency_watermark()
199 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in dce120_program_urgency_watermark()
269 REG_UPDATE(DPG_PIPE_STUTTER_CONTROL, in dce60_program_stutter_watermark()
272 REG_UPDATE(DPG_PIPE_STUTTER_CONTROL, in dce60_program_stutter_watermark()
283 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in dce120_program_stutter_watermark()
301 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_stutter_watermark()
305 REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2, in program_stutter_watermark()
308 REG_UPDATE(DPG_PIPE_STUTTER_CONTROL, in program_stutter_watermark()
760 REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT, in dce_mi_allocate_dmif()
790 REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT, in dce_mi_free_dmif()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_dccg.c66 REG_UPDATE(DPPCLK_DTO_CTRL, in dccg31_update_dpp_dto()
71 REG_UPDATE(DPPCLK_DTO_CTRL, in dccg31_update_dpp_dto()
77 REG_UPDATE(DPPCLK_DTO_CTRL, in dccg31_update_dpp_dto()
104 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
108 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
112 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
116 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
138 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_disable_dpstreamclk()
142 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_disable_dpstreamclk()
146 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_disable_dpstreamclk()
[all …]
A Ddcn31_hpo_dp_stream_encoder.c66 REG_UPDATE(DP_STREAM_ENC_CLOCK_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
70 REG_UPDATE(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
78 REG_UPDATE(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
86 REG_UPDATE(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
158 REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL, in dcn31_hpo_dp_stream_enc_dp_blank()
176 REG_UPDATE(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_disable()
180 REG_UPDATE(DP_STREAM_ENC_CLOCK_CONTROL, in dcn31_hpo_dp_stream_enc_disable()
477 REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL, in dcn31_hpo_dp_stream_enc_update_dp_info_packets()
502 REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL, in dcn31_hpo_dp_stream_enc_stop_dp_info_packets()
568 REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL, in dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet()
[all …]
A Ddcn31_dio_link_encoder.c80 REG_UPDATE(DIO_LINKA_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
83 REG_UPDATE(DIO_LINKA_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
85 REG_UPDATE(DIO_LINKA_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
90 REG_UPDATE(DIO_LINKB_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
93 REG_UPDATE(DIO_LINKB_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
95 REG_UPDATE(DIO_LINKB_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
105 REG_UPDATE(DIO_LINKC_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
115 REG_UPDATE(DIO_LINKD_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
125 REG_UPDATE(DIO_LINKE_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
135 REG_UPDATE(DIO_LINKF_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
[all …]
A Ddcn31_hpo_dp_link_encoder.c83 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_disable()
99 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
103 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
107 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
116 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
125 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
139 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
153 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
167 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
181 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_stream_encoder.c94 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, in enc1_update_generic_info_packet()
126 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
130 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
134 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
138 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
142 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
146 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
150 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
154 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
820 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, in enc1_stream_encoder_send_immediate_sdp_message()
[all …]
A Ddcn10_opp.c168 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0); in opp1_set_pixel_encoding()
177 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2); in opp1_set_pixel_encoding()
292 REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0); in opp1_program_fmt()
326 REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0); in opp1_program_stereo()
328 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, active_width); in opp1_program_stereo()
336 REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, space2_size); in opp1_program_stereo()
338 REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, space1_size); in opp1_program_stereo()
358 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, oppbuf->active_width); in opp1_program_oppbuf()
366 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, oppbuf->mso_segmentation); in opp1_program_oppbuf()
374 REG_UPDATE(OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, oppbuf->pixel_repetition); in opp1_program_oppbuf()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn302/
A Ddcn302_hwseq.c57 REG_UPDATE(DOMAIN1_PG_CONFIG, in dcn302_dpp_pg_control()
65 REG_UPDATE(DOMAIN3_PG_CONFIG, in dcn302_dpp_pg_control()
73 REG_UPDATE(DOMAIN5_PG_CONFIG, in dcn302_dpp_pg_control()
81 REG_UPDATE(DOMAIN7_PG_CONFIG, in dcn302_dpp_pg_control()
89 REG_UPDATE(DOMAIN9_PG_CONFIG, in dcn302_dpp_pg_control()
114 REG_UPDATE(DOMAIN0_PG_CONFIG, in dcn302_hubp_pg_control()
122 REG_UPDATE(DOMAIN2_PG_CONFIG, in dcn302_hubp_pg_control()
130 REG_UPDATE(DOMAIN4_PG_CONFIG, in dcn302_hubp_pg_control()
138 REG_UPDATE(DOMAIN6_PG_CONFIG, in dcn302_hubp_pg_control()
146 REG_UPDATE(DOMAIN8_PG_CONFIG, in dcn302_hubp_pg_control()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/
A Dhw_gpio.c55 REG_UPDATE(A_reg, A, gpio->store.a); in restore_registers()
107 REG_UPDATE(A_reg, A, value); in dal_hw_gpio_set_value()
114 REG_UPDATE(EN_reg, EN, ~value); in dal_hw_gpio_set_value()
151 REG_UPDATE(EN_reg, EN, 0); in dal_hw_gpio_config_mode()
152 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
157 REG_UPDATE(A_reg, A, 0); in dal_hw_gpio_config_mode()
158 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
163 REG_UPDATE(A_reg, A, 0); in dal_hw_gpio_config_mode()
164 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
168 REG_UPDATE(MASK_reg, MASK, 0); in dal_hw_gpio_config_mode()
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/linux/drivers/gpu/drm/amd/display/dc/dce120/
A Ddce120_hw_sequencer.c208 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
211 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
214 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()
219 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
222 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
225 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()
230 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
233 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
236 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_dpp.c64 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp201_cnv_setup()
65 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp201_cnv_setup()
66 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp201_cnv_setup()
67 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp201_cnv_setup()
157 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); in dpp201_cnv_setup()
158 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); in dpp201_cnv_setup()
159 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); in dpp201_cnv_setup()
160 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3); in dpp201_cnv_setup()
165 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp201_cnv_setup()
170 REG_UPDATE(CURSOR_CONTROL, in dpp201_cnv_setup()
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