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Searched refs:REG_WAIT (Results 1 – 25 of 38) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dcn302/
A Ddcn302_hwseq.c60 REG_WAIT(DOMAIN1_PG_STATUS, in dcn302_dpp_pg_control()
68 REG_WAIT(DOMAIN3_PG_STATUS, in dcn302_dpp_pg_control()
76 REG_WAIT(DOMAIN5_PG_STATUS, in dcn302_dpp_pg_control()
84 REG_WAIT(DOMAIN7_PG_STATUS, in dcn302_dpp_pg_control()
92 REG_WAIT(DOMAIN9_PG_STATUS, in dcn302_dpp_pg_control()
117 REG_WAIT(DOMAIN0_PG_STATUS, in dcn302_hubp_pg_control()
125 REG_WAIT(DOMAIN2_PG_STATUS, in dcn302_hubp_pg_control()
133 REG_WAIT(DOMAIN4_PG_STATUS, in dcn302_hubp_pg_control()
141 REG_WAIT(DOMAIN6_PG_STATUS, in dcn302_hubp_pg_control()
149 REG_WAIT(DOMAIN8_PG_STATUS, in dcn302_hubp_pg_control()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_dmcu.c96 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dce_dmcu_load_iram()
120 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dce_get_dmcu_psr_state()
144 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_dmcu_set_psr_enable()
238 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_dmcu_setup_psr()
347 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dcn10_get_dmcu_version()
497 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dcn10_dmcu_load_iram()
538 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dcn10_get_dmcu_psr_state()
566 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dcn10_dmcu_set_psr_enable()
676 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dcn10_dmcu_setup_psr()
953 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dcn10_forward_crc_window()
[all …]
A Ddce_abm.c66 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_pipe()
80 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_pipe()
106 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, in dmcu_set_backlight_level()
134 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, in dmcu_set_backlight_level()
206 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_level()
A Ddce_aux.c148 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1, in acquire_engine()
159 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0, in acquire_engine()
223 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0, in submit_channel_request()
352 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1, in get_channel_status()
A Ddce_stream_encoder.c90 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, in dce110_update_generic_info_packet()
736 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, in dce110_stream_encoder_set_throttled_vcp_size()
956 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, in dce110_stream_encoder_dp_blank()
A Ddce_panel_cntl.c249 REG_WAIT(BL_PWM_GRP1_REG_LOCK, in dce_driver_set_backlight()
A Ddce_mem_input.c745 REG_WAIT(DMIF_BUFFER_CONTROL, in dce_mi_allocate_dmif()
782 REG_WAIT(DMIF_BUFFER_CONTROL, in dce_mi_free_dmif()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_hpo_dp_stream_encoder.c73 REG_WAIT(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
81 REG_WAIT(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
107 REG_WAIT(DP_SYM32_ENC_VID_FIFO_CONTROL, in dcn31_hpo_dp_stream_enc_dp_unblank()
112 REG_WAIT(DP_SYM32_ENC_VID_FIFO_CONTROL, /* Disable Clock Ramp Adjuster FIFO */ in dcn31_hpo_dp_stream_enc_dp_unblank()
121 REG_WAIT(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, in dcn31_hpo_dp_stream_enc_dp_unblank()
126 REG_WAIT(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, in dcn31_hpo_dp_stream_enc_dp_unblank()
A Ddcn31_hwseq.c337 REG_WAIT(DOMAIN16_PG_STATUS, in dcn31_dsc_pg_control()
345 REG_WAIT(DOMAIN17_PG_STATUS, in dcn31_dsc_pg_control()
353 REG_WAIT(DOMAIN18_PG_STATUS, in dcn31_dsc_pg_control()
470 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn31_hubp_pg_control()
474 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn31_hubp_pg_control()
478 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn31_hubp_pg_control()
482 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn31_hubp_pg_control()
A Ddcn31_apg.c54 REG_WAIT(APG_CONTROL, in apg31_enable()
58 REG_WAIT(APG_CONTROL, in apg31_enable()
A Ddcn31_optc.c138 REG_WAIT(OTG_CLOCK_CONTROL, in optc31_disable_crtc()
157 REG_WAIT(OTG_CLOCK_CONTROL, in optc31_immediate_disable_crtc()
A Ddcn31_hubbub.c118 REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100); in dcn31_program_compbuf_size()
119 REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100); in dcn31_program_compbuf_size()
120 REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100); in dcn31_program_compbuf_size()
121 REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100); in dcn31_program_compbuf_size()
A Ddcn31_hpo_dp_link_encoder.c376 REG_WAIT(DP_DPHY_SYM32_STATUS, in dcn31_hpo_dp_link_enc_update_stream_allocation_table()
426 REG_WAIT(DP_DPHY_SYM32_STATUS, in dcn31_hpo_dp_link_enc_set_throttled_vcp_size()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_optc.c317 REG_WAIT(OTG_CONTROL, in optc2_align_vblanks()
364 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc2_align_vblanks()
391 REG_WAIT(OTG_CONTROL, in optc2_align_vblanks()
433 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc2_triplebuffer_lock()
A Ddcn20_hwseq.c366 REG_WAIT(DOMAIN16_PG_STATUS, in dcn20_dsc_pg_control()
437 REG_WAIT(DOMAIN1_PG_STATUS, in dcn20_dpp_pg_control()
445 REG_WAIT(DOMAIN3_PG_STATUS, in dcn20_dpp_pg_control()
453 REG_WAIT(DOMAIN5_PG_STATUS, in dcn20_dpp_pg_control()
461 REG_WAIT(DOMAIN7_PG_STATUS, in dcn20_dpp_pg_control()
469 REG_WAIT(DOMAIN9_PG_STATUS, in dcn20_dpp_pg_control()
511 REG_WAIT(DOMAIN0_PG_STATUS, in dcn20_hubp_pg_control()
519 REG_WAIT(DOMAIN2_PG_STATUS, in dcn20_hubp_pg_control()
527 REG_WAIT(DOMAIN4_PG_STATUS, in dcn20_hubp_pg_control()
535 REG_WAIT(DOMAIN6_PG_STATUS, in dcn20_hubp_pg_control()
[all …]
A Ddcn20_stream_encoder.c239 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, in enc2_update_gsp7_128_info_packet()
500 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); in enc2_stream_encoder_dp_unblank()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_stream_encoder.c83 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, in enc1_update_generic_info_packet()
663 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, in enc1_stream_encoder_set_throttled_vcp_size()
797 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, in enc1_stream_encoder_send_immediate_sdp_message()
810 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, in enc1_stream_encoder_send_immediate_sdp_message()
853 REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, in enc1_stream_encoder_send_immediate_sdp_message()
944 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, in enc1_stream_encoder_dp_blank()
A Ddcn10_optc.c471 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, in optc1_enable_optc_clock()
479 REG_WAIT(OTG_CLOCK_CONTROL, in optc1_enable_optc_clock()
544 REG_WAIT(OTG_CLOCK_CONTROL, in optc1_disable_crtc()
664 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc1_lock()
829 REG_WAIT(OTG_STATUS, in optc1_wait_for_state()
835 REG_WAIT(OTG_STATUS, in optc1_wait_for_state()
A Ddcn10_hw_sequencer.c636 REG_WAIT(DOMAIN1_PG_STATUS, in dcn10_dpp_pg_control()
644 REG_WAIT(DOMAIN3_PG_STATUS, in dcn10_dpp_pg_control()
652 REG_WAIT(DOMAIN5_PG_STATUS, in dcn10_dpp_pg_control()
660 REG_WAIT(DOMAIN7_PG_STATUS, in dcn10_dpp_pg_control()
697 REG_WAIT(DOMAIN0_PG_STATUS, in dcn10_hubp_pg_control()
705 REG_WAIT(DOMAIN2_PG_STATUS, in dcn10_hubp_pg_control()
713 REG_WAIT(DOMAIN4_PG_STATUS, in dcn10_hubp_pg_control()
721 REG_WAIT(DOMAIN6_PG_STATUS, in dcn10_hubp_pg_control()
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_optc.c55 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc3_triplebuffer_lock()
119 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc3_lock()
A Ddcn30_vpg.c72 REG_WAIT(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_OCCURED, in vpg3_update_generic_info_packet()
A Ddcn30_mpc.c157 REG_WAIT(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_STATE, 0, 10, 10); in mpc3_power_on_ogam_lut()
824 REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, 0, 1, max_retries); in mpc3_power_on_shaper_3dlut()
825 REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, 0, 1, max_retries); in mpc3_power_on_shaper_3dlut()
835 REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, 0, 1, max_retries); in mpc3_power_on_shaper_3dlut()
836 REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, 0, 1, max_retries); in mpc3_power_on_shaper_3dlut()
A Ddcn30_mmhubbub.c94 REG_WAIT(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_STATUS, 1, 20, 100); in mmhubbub3_warmup_mcif()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
A Ddcn20_clk_mgr.c175 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 100); in dcn20_update_clocks_update_dentist()
202 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 1000); in dcn20_update_clocks_update_dentist()
205 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); in dcn20_update_clocks_update_dentist()
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_optc.c59 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc201_triplebuffer_lock()

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