Searched refs:RREG32_KIQ (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu.h | 1175 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) macro
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| A D | gfx_v9_0.c | 5277 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); in gfx_v9_0_get_clockgating_state()
5282 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); in gfx_v9_0_get_clockgating_state()
5291 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); in gfx_v9_0_get_clockgating_state()
5296 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); in gfx_v9_0_get_clockgating_state()
5302 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); in gfx_v9_0_get_clockgating_state()
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| A D | sdma_v5_2.c | 1641 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); in sdma_v5_2_get_clockgating_state()
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| A D | gfx_v10_0.c | 8448 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); in gfx_v10_0_get_clockgating_state()
8453 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); in gfx_v10_0_get_clockgating_state()
8458 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); in gfx_v10_0_get_clockgating_state()
8467 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); in gfx_v10_0_get_clockgating_state()
8472 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); in gfx_v10_0_get_clockgating_state()
8477 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); in gfx_v10_0_get_clockgating_state()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| A D | vangogh_ppt.c | 2034 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK)); in vangogh_post_smu_init()
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