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Searched refs:RREG32_PCIE (Results 1 – 25 of 33) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
A Dnbio_v6_1.c169 def = data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_update_medium_grain_clock_gating()
197 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_update_medium_grain_light_sleep()
218 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_get_clockgating_state()
223 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_get_clockgating_state()
274 def = data = RREG32_PCIE(smnPCIE_CI_CNTL); in nbio_v6_1_init_registers()
311 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v6_1_program_aspm()
318 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); in nbio_v6_1_program_aspm()
328 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); in nbio_v6_1_program_aspm()
358 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); in nbio_v6_1_program_aspm()
377 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v6_1_program_aspm()
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A Dnbio_v7_4.c260 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_4_update_medium_grain_light_sleep()
281 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v7_4_get_clockgating_state()
286 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_4_get_clockgating_state()
677 def = data = RREG32_PCIE(smnRCC_BIF_STRAP2); in nbio_v7_4_program_ltr()
700 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v7_4_program_aspm()
707 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); in nbio_v7_4_program_aspm()
717 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); in nbio_v7_4_program_aspm()
722 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); in nbio_v7_4_program_aspm()
747 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); in nbio_v7_4_program_aspm()
766 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v7_4_program_aspm()
[all …]
A Dnbio_v2_3.c236 def = data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v2_3_update_medium_grain_clock_gating()
265 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v2_3_update_medium_grain_light_sleep()
286 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v2_3_get_clockgating_state()
291 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v2_3_get_clockgating_state()
377 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v2_3_enable_aspm()
430 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v2_3_program_aspm()
437 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); in nbio_v2_3_program_aspm()
447 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); in nbio_v2_3_program_aspm()
477 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); in nbio_v2_3_program_aspm()
496 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v2_3_program_aspm()
[all …]
A Dcik.c1585 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); in cik_pcie_gen3_enable()
1625 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1629 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1676 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1740 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); in cik_program_aspm()
1745 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); in cik_program_aspm()
1856 orig = data = RREG32_PCIE(ixPCIE_CNTL2); in cik_program_aspm()
1864 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); in cik_program_aspm()
1867 data = RREG32_PCIE(ixPCIE_LC_STATUS1); in cik_program_aspm()
1949 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); in cik_get_pcie_usage()
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A Dumc_v6_1.c50 rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4); in umc_v6_1_enable_umc_index_mode()
65 rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4); in umc_v6_1_disable_umc_index_mode()
80 rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4); in umc_v6_1_get_umc_index_mode_state()
119 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_1_clear_error_count_per_channel()
132 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_1_clear_error_count_per_channel()
197 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()
202 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()
212 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()
428 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_1_err_cnt_init_per_channel()
A Dumc_v6_7.c71 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
76 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
86 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
134 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_7_reset_error_count_per_channel()
147 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_7_reset_error_count_per_channel()
299 ecc_ctrl = RREG32_PCIE((ecc_ctrl_addr + in umc_v6_7_query_ras_poison_mode_per_channel()
A Dumc_v8_7.c62 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v8_7_clear_error_count_per_channel()
75 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v8_7_clear_error_count_per_channel()
122 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()
127 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()
137 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()
295 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_7_err_cnt_init_per_channel()
A Dvi.c1122 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); in vi_enable_aspm()
1146 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); in vi_program_aspm()
1160 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); in vi_program_aspm()
1165 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); in vi_program_aspm()
1232 orig = data = RREG32_PCIE(ixCPM_CONTROL); in vi_program_aspm()
1271 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); in vi_program_aspm()
1272 data1 = RREG32_PCIE(ixPCIE_LC_STATUS1); in vi_program_aspm()
1403 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); in vi_get_pcie_usage()
1417 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); in vi_get_pcie_replay_count()
1784 temp = data = RREG32_PCIE(ixPCIE_CNTL2); in vi_update_bif_medium_grain_light_sleep()
[all …]
A Dnbio_v7_0.c154 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); in nbio_v7_0_update_medium_grain_clock_gating()
192 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_update_medium_grain_light_sleep()
213 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v7_0_get_clockgating_state()
218 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_get_clockgating_state()
A Damdgpu_xgmi.c880 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]); in amdgpu_xgmi_query_ras_error_count()
887 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]); in amdgpu_xgmi_query_ras_error_count()
896 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]); in amdgpu_xgmi_query_ras_error_count()
903 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]); in amdgpu_xgmi_query_ras_error_count()
912 data = RREG32_PCIE(xgmi23_pcs_err_status_reg_aldebaran[i]); in amdgpu_xgmi_query_ras_error_count()
919 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]); in amdgpu_xgmi_query_ras_error_count()
926 data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]); in amdgpu_xgmi_query_ras_error_count()
A Dsoc15.c827 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); in soc15_get_pcie_usage()
832 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); in soc15_get_pcie_usage()
833 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); in soc15_get_pcie_usage()
876 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); in vega20_get_pcie_usage()
881 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); in vega20_get_pcie_usage()
882 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); in vega20_get_pcie_usage()
913 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); in soc15_get_pcie_replay_count()
914 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); in soc15_get_pcie_replay_count()
A Dsi.c1617 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); in si_get_pcie_usage()
1622 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); in si_get_pcie_usage()
1623 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); in si_get_pcie_usage()
1631 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); in si_get_pcie_replay_count()
1632 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED); in si_get_pcie_replay_count()
2291 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()
2472 orig = data = RREG32_PCIE(PCIE_P_CNTL); in si_program_aspm()
2635 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()
2643 data = RREG32_PCIE(PCIE_LC_STATUS1); in si_program_aspm()
A Dpsp_v3_1.c335 reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000); in psp_v3_1_smu_reload_quirk()
A Damdgpu_cgs.c64 return RREG32_PCIE(index); in amdgpu_cgs_read_ind_register()
A Dgmc_v7_0.c871 orig = data = RREG32_PCIE(ixPCIE_CNTL2); in gmc_v7_0_enable_bif_mgls()
A Damdgpu.h1186 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) macro
A Damdgpu_debugfs.c381 value = RREG32_PCIE(*pos); in amdgpu_debugfs_regs_pcie_read()
/linux/drivers/gpu/drm/radeon/
A Dr300.c94 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()
96 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()
179 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_enable()
199 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_disable()
596 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_debugfs_pcie_gart_info_show()
598 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); in rv370_debugfs_pcie_gart_info_show()
600 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); in rv370_debugfs_pcie_gart_info_show()
602 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); in rv370_debugfs_pcie_gart_info_show()
604 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); in rv370_debugfs_pcie_gart_info_show()
606 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); in rv370_debugfs_pcie_gart_info_show()
[all …]
A Dsi.c5567 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_enable_bif_mgls()
7146 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()
7289 orig = data = RREG32_PCIE(PCIE_P_CNTL); in si_program_aspm()
7452 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()
7460 data = RREG32_PCIE(PCIE_LC_STATUS1); in si_program_aspm()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Dsmu9_smumgr.c44 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu9_is_smc_ram_running()
A Dvega20_smumgr.c54 mp1_fw_flags = RREG32_PCIE(MP1_Public | in vega20_is_smc_ram_running()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0.c170 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v13_0_load_microcode()
189 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v13_0_check_fw_status()
1885 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in smu_v13_0_get_current_pcie_link_width_level()
1905 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in smu_v13_0_get_current_pcie_link_speed_level()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
A Dsmu_v12_0.c63 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v12_0_check_fw_status()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dsmu_v11_0.c195 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v11_0_load_microcode()
214 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v11_0_check_fw_status()
2126 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in smu_v11_0_get_current_pcie_link_width_level()
2146 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in smu_v11_0_get_current_pcie_link_speed_level()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega12_hwmgr.c2207 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega12_get_current_pcie_link_width_level()
2227 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in vega12_get_current_pcie_link_speed_level()

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