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Searched refs:RREG32_SOC15 (Results 1 – 25 of 78) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
A Dsmu_v11_0_i2c.c51 uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT); in smu_v11_0_i2c_set_clock_gating()
86 u32 en_stat = RREG32_SOC15(SMUIO, in smu_v11_0_i2c_enable()
106 RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR); in smu_v11_0_i2c_clear_status()
181 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_poll_tx_status()
189 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT); in smu_v11_0_i2c_poll_tx_status()
242 reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_poll_rx_status()
290 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_transmit()
413 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD); in smu_v11_0_i2c_receive()
457 reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE); in smu_v11_0_i2c_activity_done()
517 status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_fini()
[all …]
A Dmmhub_v2_0.c262 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_init_tlb_regs()
287 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_0_init_cache_regs()
300 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); in mmhub_v2_0_init_cache_regs()
331 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); in mmhub_v2_0_enable_system_domain()
454 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_gart_disable()
461 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_0_gart_disable()
579 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); in mmhub_v2_0_update_medium_grain_clock_gating()
580 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); in mmhub_v2_0_update_medium_grain_clock_gating()
638 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); in mmhub_v2_0_update_medium_grain_light_sleep()
700 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); in mmhub_v2_0_get_clockgating()
[all …]
A Dmmhub_v2_3.c189 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_init_tlb_regs()
208 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_3_init_cache_regs()
221 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); in mmhub_v2_3_init_cache_regs()
252 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); in mmhub_v2_3_enable_system_domain()
383 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_gart_disable()
390 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_3_gart_disable()
494 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); in mmhub_v2_3_update_medium_grain_clock_gating()
586 data = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); in mmhub_v2_3_get_clockgating()
587 data1 = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL); in mmhub_v2_3_get_clockgating()
588 data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL); in mmhub_v2_3_get_clockgating()
[all …]
A Dvcn_v1_0.c231 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) { in vcn_v1_0_hw_fini()
445 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
461 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
471 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
494 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
585 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
594 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
801 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); in vcn_v1_0_start_spg_mode()
814 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); in vcn_v1_0_start_spg_mode()
1170 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); in vcn_v1_0_stop_dpg_mode()
[all …]
A Dsmuio_v13_0.c48 def = data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); in smuio_v13_0_update_rom_clock_gating()
69 data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); in smuio_v13_0_get_clock_gating_state()
85 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_die_id()
102 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_socket_id()
119 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_is_host_gpu_xgmi_supported()
A Ddf_v1_7.c49 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); in df_v1_7_enable_broadcast_mode()
61 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); in df_v1_7_get_fb_channel_number()
86 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
91 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
107 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_get_clockgating_state()
A Dmmhub_v1_0.c39 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); in mmhub_v1_0_get_fb_location()
40 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP); in mmhub_v1_0_get_fb_location()
140 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_init_tlb_regs()
163 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); in mmhub_v1_0_init_cache_regs()
174 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); in mmhub_v1_0_init_cache_regs()
200 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); in mmhub_v1_0_enable_system_domain()
350 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_gart_disable()
360 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); in mmhub_v1_0_gart_disable()
514 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); in mmhub_v1_0_update_medium_grain_light_sleep()
556 data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); in mmhub_v1_0_get_clockgating()
[all …]
A Dhdp_v5_0.c62 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_mem_power_gating()
63 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_update_mem_power_gating()
153 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_medium_grain_clock_gating()
189 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_get_clockgating_state()
199 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_get_clockgating_state()
212 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); in hdp_v5_0_init_registers()
A Djpeg_v3_0.c54 u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING); in jpeg_v3_0_early_init()
169 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS)) in jpeg_v3_0_hw_fini()
221 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); in jpeg_v3_0_disable_clock_gating()
231 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v3_0_disable_clock_gating()
239 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); in jpeg_v3_0_disable_clock_gating()
251 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v3_0_enable_clock_gating()
365 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v3_0_start()
410 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v3_0_dec_ring_get_rptr()
427 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v3_0_dec_ring_get_wptr()
454 ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) & in jpeg_v3_0_is_idle()
A Dgfxhub_v1_1.c53 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL_ALDE); in gfxhub_v1_1_get_xgmi_info()
55 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE), in gfxhub_v1_1_get_xgmi_info()
60 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL); in gfxhub_v1_1_get_xgmi_info()
62 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE), in gfxhub_v1_1_get_xgmi_info()
A Dnbio_v7_4.c115 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE); in nbio_v7_4_get_rev_id()
117 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); in nbio_v7_4_get_rev_id()
136 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); in nbio_v7_4_get_memsize()
237 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); in nbio_v7_4_ih_doorbell_range()
297 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); in nbio_v7_4_ih_control()
380 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); in nbio_v7_4_handle_ras_controller_intr_no_bifring()
436 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); in nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring()
467 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE); in nbio_v7_4_set_ras_controller_irq_state()
469 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); in nbio_v7_4_set_ras_controller_irq_state()
512 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE); in nbio_v7_4_set_ras_err_event_athub_irq_state()
[all …]
A Dvcn_v2_0.c266 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) in vcn_v2_0_hw_fini()
488 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
497 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v2_0_disable_clock_gating()
520 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
648 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
657 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
954 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); in vcn_v2_0_start()
962 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); in vcn_v2_0_start()
1104 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); in vcn_v2_0_stop_dpg_mode()
1107 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); in vcn_v2_0_stop_dpg_mode()
[all …]
A Dnbio_v2_3.c86 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); in nbio_v2_3_get_rev_id()
105 return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); in nbio_v2_3_get_memsize()
189 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE); in nbio_v2_3_ih_doorbell_range()
213 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); in nbio_v2_3_ih_control()
410 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2); in nbio_v2_3_program_ltr()
452 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); in nbio_v2_3_program_aspm()
458 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5); in nbio_v2_3_program_aspm()
485 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); in nbio_v2_3_program_aspm()
491 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5); in nbio_v2_3_program_aspm()
553 reg = RREG32_SOC15(NBIO, 0, mmBIF_RB_CNTL); in nbio_v2_3_clear_doorbell_interrupt()
[all …]
A Dgfxhub_v2_1.c110 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_1_get_fb_location()
120 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_1_get_mc_fb_offset()
192 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_init_tlb_regs()
217 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_1_init_cache_regs()
230 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_1_init_cache_regs()
261 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); in gfxhub_v2_1_enable_system_domain()
392 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_gart_disable()
420 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_1_set_fault_enable_default()
529 RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE), in gfxhub_v2_1_get_xgmi_info()
548 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); in gfxhub_v2_1_utcl2_harvest()
[all …]
A Dmes_v10_1.c420 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); in mes_v10_1_enable()
429 data = RREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL); in mes_v10_1_enable()
438 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); in mes_v10_1_enable()
503 data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL); in mes_v10_1_load_microcode()
523 data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL); in mes_v10_1_load_microcode()
614 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); in mes_v10_1_mqd_init()
651 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); in mes_v10_1_mqd_init()
661 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); in mes_v10_1_mqd_init()
715 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); in mes_v10_1_mqd_init()
734 data = RREG32_SOC15(GC, 0, mmCP_HQD_VMID); in mes_v10_1_queue_init_register()
[all …]
A Dvcn_v2_5.c324 RREG32_SOC15(VCN, i, mmUVD_STATUS))) in vcn_v2_5_hw_fini()
547 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
556 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
582 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
712 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
721 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
946 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); in vcn_v2_5_start()
955 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); in vcn_v2_5_start()
1008 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v2_5_start()
1113 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); in vcn_v2_5_mmsch_start()
[all …]
A Dvcn_v3_0.c371 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { in vcn_v3_0_hw_fini()
685 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
694 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); in vcn_v3_0_disable_clock_gating()
720 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
1119 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_start()
1125 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); in vcn_v3_0_start()
1133 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); in vcn_v3_0_start()
1434 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); in vcn_v3_0_start_sriov()
1531 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); in vcn_v3_0_stop()
1555 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_stop()
[all …]
A Dathub_v2_0.c42 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_0_update_medium_grain_clock_gating()
63 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_0_update_medium_grain_light_sleep()
100 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_0_get_clockgating()
A Dathub_v2_1.c38 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_1_update_medium_grain_clock_gating()
55 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_1_update_medium_grain_light_sleep()
92 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_1_get_clockgating()
A Djpeg_v2_5.c63 harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING); in jpeg_v2_5_early_init()
199 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS)) in jpeg_v2_5_hw_fini()
252 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); in jpeg_v2_5_disable_clock_gating()
262 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); in jpeg_v2_5_disable_clock_gating()
269 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); in jpeg_v2_5_disable_clock_gating()
281 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); in jpeg_v2_5_enable_clock_gating()
339 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR); in jpeg_v2_5_start()
387 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR); in jpeg_v2_5_dec_ring_get_rptr()
404 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR); in jpeg_v2_5_dec_ring_get_wptr()
471 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) & in jpeg_v2_5_is_idle()
A Dathub_v1_0.c37 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_update_medium_grain_clock_gating()
53 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_update_medium_grain_light_sleep()
97 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v1_0_get_clockgating()
A Dpsp_v13_0.c94 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); in psp_v13_0_is_sos_alive()
213 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), in psp_v13_0_bootloader_load_sos()
365 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); in psp_v13_0_ring_get_wptr()
367 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); in psp_v13_0_ring_get_wptr()
408 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); in psp_v13_0_load_usbc_pd_fw()
437 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); in psp_v13_0_read_usbc_pd_fw()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega20_thermal.c95 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega20_fan_ctrl_set_static_mode()
98 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega20_fan_ctrl_set_static_mode()
124 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_get_fan_speed_pwm()
126 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), in vega20_fan_ctrl_get_fan_speed_pwm()
152 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_set_fan_speed_pwm()
163 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), in vega20_fan_ctrl_set_fan_speed_pwm()
206 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), in vega20_fan_ctrl_set_fan_speed_rpm()
223 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); in vega20_thermal_get_temperature()
260 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); in vega20_thermal_set_temperature_range()
A Dvega10_thermal.c105 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), in vega10_fan_ctrl_get_fan_speed_rpm()
133 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
136 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
142 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
145 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
162 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
166 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
275 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), in vega10_fan_ctrl_set_fan_speed_pwm()
390 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); in vega10_thermal_set_temperature_range()
416 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), in vega10_thermal_initialize()
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Dsmu9_smumgr.c74 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103); in smu9_wait_for_response()
83 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu9_wait_for_response()
171 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102); in smu9_get_argument()
173 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu9_get_argument()

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