| /linux/arch/arm/mach-s3c/ |
| A D | sleep-s3c2410.S | 38 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
39 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
50 streq r7, [r4] @ SDRAM sleep command
51 streq r8, [r5] @ SDRAM power-down config
|
| /linux/arch/arm/mach-pxa/ |
| A D | sleep.S | 54 @ prepare SDRAM refresh settings
58 @ enable SDRAM self-refresh mode
95 @ prepare SDRAM refresh settings
99 @ enable SDRAM self-refresh mode
106 @ We keep the change-down close to the actual suspend on SDRAM
159 @ external accesses after SDRAM is put in self-refresh mode
165 @ put SDRAM into self-refresh
|
| /linux/Documentation/devicetree/bindings/arm/altera/ |
| A D | socfpga-sdram-edac.txt | 1 Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
2 The EDAC accesses a range of registers in the SDRAM controller.
7 - interrupts : Should contain the SDRAM ECC IRQ in the
|
| A D | socfpga-sdram-controller.txt | 1 Altera SOCFPGA SDRAM Controller
5 syscon is required by the Altera SOCFPGA SDRAM EDAC.
|
| /linux/Documentation/driver-api/memory-devices/ |
| A D | ti-emif.rst | 4 TI EMIF SDRAM Controller Driver
29 SoCs. EMIF is an SDRAM controller that, based on its revision,
30 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
|
| /linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| A D | jedec,lpddr2.yaml | 7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
32 Revision 1 value of SDRAM chip. Obtained from device datasheet.
38 Revision 2 value of SDRAM chip. Obtained from device datasheet.
43 Density in megabits of SDRAM chip. Obtained from device datasheet.
59 IO bus width in bits of SDRAM chip. Obtained from device datasheet.
|
| /linux/drivers/memory/ |
| A D | Kconfig | 20 Data from JEDEC specs for DDR SDRAM memories,
23 DDR SDRAM controllers.
34 bool "Atmel (Multi-port DDR-)SDRAM Controller"
39 This driver is for Atmel SDRAM Controller or Atmel Multi-port
40 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
98 SoCs. EMIF is an SDRAM controller that, based on its revision,
99 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
|
| /linux/Documentation/devicetree/bindings/arm/omap/ |
| A D | dmm.txt | 4 SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory
5 accesses such as priority generation amongst initiators, configuration of SDRAM
|
| /linux/Documentation/devicetree/bindings/memory-controllers/ti/ |
| A D | emif.txt | 1 * EMIF family of TI SDRAM controllers
3 EMIF - External Memory Interface - is an SDRAM controller used in
57 has capability for generating SDRAM temperature alerts
|
| /linux/arch/arm/boot/dts/ |
| A D | r7s9210-rza2mevb.dts | 8 * Hence the 64 MiB of SDRAM on the sub-board needs to be enabled, which has
22 * SW6 SW6-1 set to SDRAM
84 reg = <0x0c000000 0x04000000>; /* SDRAM */
|
| /linux/arch/arm/mach-omap2/ |
| A D | Kconfig | 149 bool "OMAP2 SDRAM Controller support"
212 access SDRAM during CORE DVFS, select Y here. This should boost
213 SDRAM performance at lower CORE OPPs. There are relatively few
|
| /linux/drivers/video/fbdev/omap/ |
| A D | Kconfig | 53 bool "Set DMA SDRAM access priority high"
57 (SDRAM) this will speed up graphics DMA operations.
|
| /linux/arch/arm/mach-omap1/ |
| A D | sleep.S | 81 @ prepare to put SDRAM into self-refresh manually
166 @ prepare to put SDRAM into self-refresh manually
236 @ Prepare to put SDRAM into self-refresh manually
|
| /linux/Documentation/devicetree/bindings/fpga/ |
| A D | altera-fpga2sdram-bridge.txt | 1 Altera FPGA To SDRAM Bridge Driver
|
| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| A D | mediatek,mt7621-memc.yaml | 7 title: MT7621 SDRAM controller
|
| A D | marvell,mvebu-sdram-controller.yaml | 7 title: Marvell MVEBU SDRAM controller
|
| A D | nvidia,tegra20-emc.yaml | 15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
17 various performance-affecting settings beyond the obvious SDRAM configuration
|
| /linux/Documentation/devicetree/bindings/clock/ |
| A D | mvebu-core-clock.txt | 30 3 = hclk (SDRAM Controller Internal Clock)
31 4 = dclk (SDRAM Interface Clock)
|
| /linux/arch/arm/mach-lpc32xx/ |
| A D | suspend.S | 52 @ Wait for SDRAM busy status to go busy and then idle
|
| /linux/Documentation/arm/stm32/ |
| A D | stm32f429-overview.rst | 13 - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
|
| A D | stm32h743-overview.rst | 13 - FMC controller to connect SDRAM, NOR and NAND memories
|
| A D | stm32h750-overview.rst | 13 - FMC controller to connect SDRAM, NOR and NAND memories
|
| A D | stm32mp13-overview.rst | 19 - FMC controller to connect SDRAM, NOR and NAND memories
|
| A D | stm32f746-overview.rst | 13 - FMC controller to connect SDRAM, NOR and NAND memories
|
| A D | stm32f769-overview.rst | 13 - FMC controller to connect SDRAM, NOR and NAND memories
|