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Searched refs:SMU__NUM_PCIE_DPM_LEVELS (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Dci_smumgr.h29 #define SMU__NUM_PCIE_DPM_LEVELS 8 macro
/linux/drivers/gpu/drm/radeon/
A Dsmu7.h44 #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes.
A Dkv_dpm.h29 #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */ macro
A Dci_dpm.h32 #define SMU__NUM_PCIE_DPM_LEVELS 8 macro
/linux/drivers/gpu/drm/amd/pm/inc/
A Dsmu71.h30 #define SMU__NUM_PCIE_DPM_LEVELS 8 macro
64 #define SMU71_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS
A Dsmu7.h44 #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes.
A Dsmu72.h34 #define SMU__NUM_PCIE_DPM_LEVELS 8 macro
112 #define SMU72_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lane…
A Dsmu73.h96 #define SMU__NUM_PCIE_DPM_LEVELS 8 macro
111 #define SMU73_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lane…
A Dsmu75.h43 #define SMU__NUM_PCIE_DPM_LEVELS 8 macro
58 #define SMU75_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS
A Dsmu74.h35 #define SMU__NUM_PCIE_DPM_LEVELS 8 macro
137 #define SMU74_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lane…
/linux/drivers/gpu/drm/amd/pm/powerplay/
A Dkv_dpm.h29 #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */ macro

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