Home
last modified time | relevance | path

Searched refs:SOC15_WAIT_ON_RREG (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dvcn_v1_0.c1124 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v1_0_stop_spg_mode()
1133 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v1_0_stop_spg_mode()
1165 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_stop_dpg_mode()
1171 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
1174 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
1182 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_stop_dpg_mode()
1227 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_pause_dpg_mode()
1235 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, in vcn_v1_0_pause_dpg_mode()
1257 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_pause_dpg_mode()
1296 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, in vcn_v1_0_pause_dpg_mode()
[all …]
A Dvcn_v2_0.c714 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, in vcn_v2_0_disable_static_power_gating()
728 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF); in vcn_v2_0_disable_static_power_gating()
781 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF); in vcn_v2_0_enable_static_power_gating()
1100 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
1105 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1108 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1113 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
1144 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_0_stop()
1155 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_0_stop()
1216 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, in vcn_v2_0_pause_dpg_mode()
[all …]
A Dvcn_v2_5.c580 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v2_5_disable_clock_gating()
1296 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1301 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1304 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1309 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1341 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1352 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1413 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, in vcn_v2_5_pause_dpg_mode()
1447 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, in vcn_v2_5_pause_dpg_mode()
1453 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, in vcn_v2_5_pause_dpg_mode()
[all …]
A Dvcn_v3_0.c597 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, in vcn_v3_0_disable_static_power_gating()
615 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); in vcn_v3_0_disable_static_power_gating()
718 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v3_0_disable_clock_gating()
1480 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1485 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1493 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1526 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v3_0_stop()
1536 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v3_0_stop()
1603 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, in vcn_v3_0_pause_dpg_mode()
1644 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, in vcn_v3_0_pause_dpg_mode()
[all …]
A Djpeg_v3_0.c269 r = SOC15_WAIT_ON_RREG(JPEG, 0, in jpeg_v3_0_disable_static_power_gating()
304 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, in jpeg_v3_0_enable_static_power_gating()
465 return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, in jpeg_v3_0_wait_for_idle()
A Djpeg_v2_0.c215 r = SOC15_WAIT_ON_RREG(JPEG, 0, in jpeg_v2_0_disable_power_gating()
246 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, in jpeg_v2_0_enable_power_gating()
668 ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, in jpeg_v2_0_wait_for_idle()
A Dsoc15_common.h76 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \ macro
A Djpeg_v2_5.c488 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS, in jpeg_v2_5_wait_for_idle()

Completed in 22 milliseconds