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Searched refs:SRII (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clock_source.h60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
90 SRII(PHASE, DP_DTO, 0),\
91 SRII(PHASE, DP_DTO, 1),\
[all …]
A Ddce_hwseq.h54 SRII(BLND_CONTROL, BLND, 0), \
55 SRII(BLND_CONTROL, BLND, 1), \
56 SRII(BLND_CONTROL, BLND, 2), \
57 SRII(BLND_CONTROL, BLND, 3), \
58 SRII(BLND_CONTROL, BLND, 4), \
59 SRII(BLND_CONTROL, BLND, 5)
71 SRII(PIXEL_RATE_CNTL, blk, 5)
75 SRII(PIXEL_RATE_CNTL, blk, 1)
91 SRII(PIXEL_RATE_CNTL, blk, 5)
114 SRII(BLND_CONTROL, BLND, 0),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_mpc.h35 SRII(MPCC_TOP_GAIN, MPCC, inst),\
36 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
66 SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
70 SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst)
74 SRII(CSC_MODE, MPC_OUT, inst),\
75 SRII(CSC_C11_C12_A, MPC_OUT, inst),\
76 SRII(CSC_C33_C34_A, MPC_OUT, inst),\
77 SRII(CSC_C11_C12_B, MPC_OUT, inst),\
78 SRII(CSC_C33_C34_B, MPC_OUT, inst),\
79 SRII(DENORM_CONTROL, MPC_OUT, inst),\
[all …]
A Ddcn20_dwb.h49 #define SRII(reg_name, block, id)\ macro
A Ddcn20_resource.c507 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_mpc.h47 SRII(MPCC_TOP_GAIN, MPCC, inst),\
48 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
50 SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
109 SRII(CSC_MODE, MPC_OUT, inst),\
110 SRII(CSC_C11_C12_A, MPC_OUT, inst),\
111 SRII(CSC_C33_C34_A, MPC_OUT, inst),\
112 SRII(CSC_C11_C12_B, MPC_OUT, inst),\
113 SRII(CSC_C33_C34_B, MPC_OUT, inst),\
114 SRII(DENORM_CONTROL, MPC_OUT, inst),\
124 SRII(SHAPER_CONTROL, MPC_RMU, inst),\
[all …]
A Ddcn30_resource.c262 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_mpc.h34 SRII(MPCC_TOP_SEL, MPCC, inst),\
35 SRII(MPCC_BOT_SEL, MPCC, inst),\
36 SRII(MPCC_CONTROL, MPCC, inst),\
37 SRII(MPCC_STATUS, MPCC, inst),\
38 SRII(MPCC_OPP_ID, MPCC, inst),\
39 SRII(MPCC_BG_G_Y, MPCC, inst),\
40 SRII(MPCC_BG_R_CR, MPCC, inst),\
41 SRII(MPCC_BG_B_CB, MPCC, inst),\
42 SRII(MPCC_SM_CONTROL, MPCC, inst),\
43 SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
[all …]
A Ddcn10_dwb.h45 #define SRII(reg_name, block, id)\ macro
A Ddcn10_resource.c181 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_resource.c287 #define SRII(reg_name, block, id)\ macro
828 SRII(PIXEL_RATE_CNTL, OTG, 0), \
829 SRII(PIXEL_RATE_CNTL, OTG, 1),\
830 SRII(PIXEL_RATE_CNTL, OTG, 2),\
831 SRII(PIXEL_RATE_CNTL, OTG, 3),\
832 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
833 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
834 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
835 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
A Ddcn31_hpo_dp_link_encoder.h68 SRII(RDPCSTX_PHY_CNTL6, RDPCSTX, id)
/linux/drivers/gpu/drm/amd/display/dc/dce100/
A Ddce100_resource.c489 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/dce120/
A Ddce120_resource.c772 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_resource.c263 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/dce112/
A Ddce112_resource.c519 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/dce60/
A Ddce60_resource.c607 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/dce80/
A Ddce80_resource.c612 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_resource.c541 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
A Ddcn301_resource.c130 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/dcn302/
A Ddcn302_resource.c326 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/dcn303/
A Ddcn303_resource.c303 #define SRII(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_resource.c338 #define SRII(reg_name, block, id)\ macro

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