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Searched refs:THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/thm/
A Dthm_11_0_2_sh_mask.h48 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT macro
A Dthm_10_0_sh_mask.h129 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT macro
A Dthm_13_0_2_sh_mask.h281 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT macro
A Dthm_9_0_sh_mask.h273 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT macro
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega12_thermal.c214 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); in vega12_thermal_enable_alert()
A Dvega20_thermal.c285 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); in vega20_thermal_enable_alert()
A Dvega10_thermal.c453 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); in vega10_thermal_enable_alert()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0.c1240 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); in smu_v13_0_set_irq_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
A Dsmu_8_0_sh_mask.h152 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 macro
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dsmu_v11_0.c1414 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); in smu_v11_0_set_irq_state()

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