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Searched refs:TI_CLK_MUX (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/clk/ti/
A Dclk-7xx-compat.c55 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
56 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
77 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
82 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
87 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
92 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
103 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
166 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
167 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
265 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
[all …]
A Dclk-7xx.c39 { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
76 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
98 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
103 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
108 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
124 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
156 { 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL },
221 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
322 { 24, TI_CLK_MUX, dra7_gpu_core_mux_parents, NULL, },
323 { 26, TI_CLK_MUX, dra7_gpu_hyd_mux_parents, NULL, },
[all …]
A Dclk-44xx.c74 { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
87 { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
334 { 24, TI_CLK_MUX, omap4_sgx_clk_mux_parents, NULL },
350 { 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
355 { 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
473 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
478 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
483 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
488 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
493 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
[all …]
A Dclk-54xx.c67 { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
68 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
80 { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
81 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
93 { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
94 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
106 { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
107 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
118 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
374 { 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
[all …]
A Dclk-33xx-compat.c149 { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
150 { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
A Dclk-33xx.c191 { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
192 { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
A Dclock.h49 TI_CLK_MUX, enumerator
A Dclkctrl.c452 case TI_CLK_MUX: in _ti_clkctrl_setup_subclks()

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