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Searched refs:WREG32_PCIE (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dnbio_v6_1.c189 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v6_1_update_medium_grain_clock_gating()
209 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v6_1_update_medium_grain_light_sleep()
278 WREG32_PCIE(smnPCIE_CI_CNTL, data); in nbio_v6_1_init_registers()
294 WREG32_PCIE(smnRCC_BIF_STRAP2, data); in nbio_v6_1_program_ltr()
316 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v6_1_program_aspm()
321 WREG32_PCIE(smnPCIE_LC_CNTL7, data); in nbio_v6_1_program_aspm()
331 WREG32_PCIE(smnPCIE_LC_CNTL3, data); in nbio_v6_1_program_aspm()
337 WREG32_PCIE(smnRCC_BIF_STRAP3, data); in nbio_v6_1_program_aspm()
362 WREG32_PCIE(smnPCIE_LC_CNTL6, data); in nbio_v6_1_program_aspm()
382 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v6_1_program_aspm()
[all …]
A Dnbio_v7_4.c272 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_4_update_medium_grain_light_sleep()
680 WREG32_PCIE(smnRCC_BIF_STRAP2, data); in nbio_v7_4_program_ltr()
705 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v7_4_program_aspm()
710 WREG32_PCIE(smnPCIE_LC_CNTL7, data); in nbio_v7_4_program_aspm()
720 WREG32_PCIE(smnPCIE_LC_CNTL3, data); in nbio_v7_4_program_aspm()
726 WREG32_PCIE(smnRCC_BIF_STRAP3, data); in nbio_v7_4_program_aspm()
731 WREG32_PCIE(smnRCC_BIF_STRAP5, data); in nbio_v7_4_program_aspm()
751 WREG32_PCIE(smnPCIE_LC_CNTL6, data); in nbio_v7_4_program_aspm()
759 WREG32_PCIE(smnRCC_BIF_STRAP3, data); in nbio_v7_4_program_aspm()
771 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v7_4_program_aspm()
[all …]
A Dnbio_v2_3.c254 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v2_3_update_medium_grain_clock_gating()
277 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v2_3_update_medium_grain_light_sleep()
361 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); in nbio_v2_3_init_registers()
401 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v2_3_enable_aspm()
435 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v2_3_program_aspm()
440 WREG32_PCIE(smnPCIE_LC_CNTL7, data); in nbio_v2_3_program_aspm()
450 WREG32_PCIE(smnPCIE_LC_CNTL3, data); in nbio_v2_3_program_aspm()
481 WREG32_PCIE(smnPCIE_LC_CNTL6, data); in nbio_v2_3_program_aspm()
501 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v2_3_program_aspm()
506 WREG32_PCIE(smnPCIE_LC_CNTL3, data); in nbio_v2_3_program_aspm()
[all …]
A Dumc_v8_7.c67 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
71 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
80 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
84 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
125 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_query_correctable_error_count()
135 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_query_correctable_error_count()
301 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_err_cnt_init_per_channel()
303 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_7_CE_CNT_INIT); in umc_v8_7_err_cnt_init_per_channel()
308 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_err_cnt_init_per_channel()
309 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_7_CE_CNT_INIT); in umc_v8_7_err_cnt_init_per_channel()
A Dumc_v6_1.c56 WREG32_PCIE(rsmu_umc_addr * 4, rsmu_umc_val); in umc_v6_1_enable_umc_index_mode()
71 WREG32_PCIE(rsmu_umc_addr * 4, rsmu_umc_val); in umc_v6_1_disable_umc_index_mode()
124 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
128 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
137 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
141 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
200 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_query_correctable_error_count()
210 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_query_correctable_error_count()
434 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_err_cnt_init_per_channel()
436 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V6_1_CE_CNT_INIT); in umc_v6_1_err_cnt_init_per_channel()
[all …]
A Dcik.c1627 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1631 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1678 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1733 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); in cik_program_aspm()
1738 WREG32_PCIE(ixPCIE_LC_CNTL3, data); in cik_program_aspm()
1743 WREG32_PCIE(ixPCIE_P_CNTL, data); in cik_program_aspm()
1756 WREG32_PCIE(ixPCIE_LC_CNTL, data); in cik_program_aspm()
1816 WREG32_PCIE(ixPCIE_LC_CNTL2, data); in cik_program_aspm()
1853 WREG32_PCIE(ixPCIE_LC_CNTL, data); in cik_program_aspm()
1861 WREG32_PCIE(ixPCIE_CNTL2, data); in cik_program_aspm()
[all …]
A Dumc_v6_7.c74 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_7_query_correctable_error_count()
84 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_7_query_correctable_error_count()
139 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
143 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
152 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
156 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
A Dvi.c1130 WREG32_PCIE(ixPCIE_LC_CNTL, data); in vi_enable_aspm()
1151 WREG32_PCIE(ixPCIE_LC_CNTL, data); in vi_program_aspm()
1163 WREG32_PCIE(ixPCIE_LC_CNTL3, data); in vi_program_aspm()
1168 WREG32_PCIE(ixPCIE_P_CNTL, data); in vi_program_aspm()
1188 WREG32_PCIE(ixPCIE_LC_CNTL6, data); in vi_program_aspm()
1236 WREG32_PCIE(ixCPM_CONTROL, data); in vi_program_aspm()
1252 WREG32_PCIE(ixPCIE_LC_CNTL7, data); in vi_program_aspm()
1257 WREG32_PCIE(ixPCIE_HW_DEBUG, data); in vi_program_aspm()
1265 WREG32_PCIE(ixPCIE_LC_CNTL2, data); in vi_program_aspm()
1279 WREG32_PCIE(ixPCIE_LC_CNTL, data); in vi_program_aspm()
[all …]
A Dnbio_v7_0.c162 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); in nbio_v7_0_update_medium_grain_clock_gating()
204 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_0_update_medium_grain_light_sleep()
A Dsoc15.c809 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); in soc15_get_pcie_usage()
815 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); in soc15_get_pcie_usage()
824 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); in soc15_get_pcie_usage()
858 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); in vega20_get_pcie_usage()
864 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); in vega20_get_pcie_usage()
873 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); in vega20_get_pcie_usage()
A Dsi.c1599 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); in si_get_pcie_usage()
1605 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); in si_get_pcie_usage()
1614 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); in si_get_pcie_usage()
2475 WREG32_PCIE(PCIE_P_CNTL, data); in si_program_aspm()
2638 WREG32_PCIE(PCIE_CNTL2, data); in si_program_aspm()
A Damdgpu_xgmi.c787 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF); in pcs_clear_status()
788 WREG32_PCIE(pcs_status_reg, 0); in pcs_clear_status()
A Damdgpu_cgs.c92 return WREG32_PCIE(index, value); in amdgpu_cgs_write_ind_register()
A Dgmc_v7_0.c886 WREG32_PCIE(ixPCIE_CNTL2, data); in gmc_v7_0_enable_bif_mgls()
A Damdgpu.h1187 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) macro
A Damdgpu_debugfs.c448 WREG32_PCIE(*pos, value); in amdgpu_debugfs_regs_pcie_write()
/linux/drivers/gpu/drm/radeon/
A Dr300.c97 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_tlb_flush()
166 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable()
169 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); in rv370_pcie_gart_enable()
170 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_enable()
171 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); in rv370_pcie_gart_enable()
178 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); in rv370_pcie_gart_enable()
182 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable()
195 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); in rv370_pcie_gart_disable()
196 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); in rv370_pcie_gart_disable()
197 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_disable()
[all …]
A Dsi.c5577 WREG32_PCIE(PCIE_CNTL2, data); in si_enable_bif_mgls()
7292 WREG32_PCIE(PCIE_P_CNTL, data); in si_program_aspm()
7455 WREG32_PCIE(PCIE_CNTL2, data); in si_program_aspm()
A Drv6xx_dpm.c135 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv6xx_enable_pll_sleep_in_l1()
A Drv770_dpm.c128 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv770_enable_pll_sleep_in_l1()
A Dradeon.h2558 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) macro
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0.c160 WREG32_PCIE(addr_start, src[i]); in smu_v13_0_load_microcode()
164 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v13_0_load_microcode()
166 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v13_0_load_microcode()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dsmu_v11_0.c185 WREG32_PCIE(addr_start, src[i]); in smu_v11_0_load_microcode()
189 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v11_0_load_microcode()
191 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v11_0_load_microcode()

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