Searched refs:X86_CONFIG (Results 1 – 4 of 4) sorted by relevance
| /linux/arch/x86/kernel/cpu/resctrl/ |
| A D | pseudo_lock.c | 1067 perf_miss_attr.config = X86_CONFIG(.event = 0xd1, in measure_l2_residency()
1069 perf_hit_attr.config = X86_CONFIG(.event = 0xd1, in measure_l2_residency()
1106 perf_hit_attr.config = X86_CONFIG(.event = 0x2e, in measure_l3_residency()
1108 perf_miss_attr.config = X86_CONFIG(.event = 0x2e, in measure_l3_residency()
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| /linux/arch/x86/events/intel/ |
| A D | core.c | 3604 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); in intel_pebs_aliases_core2()
4214 X86_CONFIG(.event=0xc0, .umask=0x01)) { in bdw_limit_period()
5705 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5708 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
5862 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5865 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
5902 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5905 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5943 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6135 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); in intel_pmu_init()
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| /linux/arch/x86/events/zhaoxin/ |
| A D | core.c | 564 X86_CONFIG(.event = 0x01, .umask = 0x01, .inv = 0x01, .cmask = 0x01); in zhaoxin_pmu_init()
567 X86_CONFIG(.event = 0x0f, .umask = 0x04, .inv = 0, .cmask = 0); in zhaoxin_pmu_init()
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| /linux/arch/x86/events/ |
| A D | perf_event.h | 628 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value macro
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