Searched refs:XAXIDMA_TX_CR_OFFSET (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/net/ethernet/ni/ |
| A D | nixge.c | 26 #define XAXIDMA_TX_CR_OFFSET 0x00 /* Channel control */ macro
356 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_hw_dma_bd_init()
366 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr); in nixge_hw_dma_bd_init()
384 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, in nixge_hw_dma_bd_init()
415 __nixge_device_reset(priv, XAXIDMA_TX_CR_OFFSET); in nixge_device_reset()
797 __nixge_device_reset(lp, XAXIDMA_TX_CR_OFFSET); in nixge_dma_err_handler()
834 cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET); in nixge_dma_err_handler()
844 nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET, cr); in nixge_dma_err_handler()
861 cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET); in nixge_dma_err_handler()
862 nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET, in nixge_dma_err_handler()
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| /linux/drivers/net/ethernet/xilinx/ |
| A D | xilinx_axienet_main.c | 312 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_dma_bd_init()
322 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); in axienet_dma_bd_init()
339 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_dma_bd_init()
340 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, in axienet_dma_bd_init()
932 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_tx_irq()
1131 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_stop()
1133 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); in axienet_stop()
1777 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_dma_err_handler()
1787 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); in axienet_dma_err_handler()
1804 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_dma_err_handler()
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| A D | xilinx_axienet.h | 74 #define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */ macro
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