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Searched refs:XCHAL_DEBUGLEVEL (Results 1 – 14 of 14) sorted by relevance

/linux/arch/xtensa/include/asm/
A Dirqflags.h30 #if defined(CONFIG_DEBUG_MISC) && (LOCKLEVEL | TOPLEVEL) >= XCHAL_DEBUGLEVEL in arch_local_irq_save()
/linux/arch/xtensa/boot/boot-elf/
A Dbootstrap.S61 rsil a0, XCHAL_DEBUGLEVEL-1
/linux/arch/xtensa/kernel/
A Dentry.S81 #if defined(CONFIG_DEBUG_KERNEL) && (LOCKLEVEL | TOPLEVEL) >= XCHAL_DEBUGLEVEL
802 rsr a0, SREG_EPS + XCHAL_DEBUGLEVEL
808 rsr a2, SREG_EPC + XCHAL_DEBUGLEVEL
831 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
884 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
885 rfi XCHAL_DEBUGLEVEL
905 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
906 rfi XCHAL_DEBUGLEVEL
A Dsetup.c643 XCHAL_DEBUGLEVEL); in c_show()
A Dtraps.c404 __asm__ __volatile__("wsr %0, excsave" __stringify(XCHAL_DEBUGLEVEL) in trap_init_debug()
A Dvectors.S615 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
/linux/arch/xtensa/variants/fsf/include/variant/
A Dcore.h225 #define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */ macro
/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
A Dcore.h240 #define XCHAL_DEBUGLEVEL 2 /* debug interrupt level */ macro
/linux/arch/xtensa/variants/dc232b/include/variant/
A Dcore.h237 #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ macro
/linux/arch/xtensa/variants/dc233c/include/variant/
A Dcore.h285 #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ macro
/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
A Dcore.h309 #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ macro
/linux/arch/xtensa/variants/de212/include/variant/
A Dcore.h370 #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ macro
/linux/arch/xtensa/variants/test_kc705_be/include/variant/
A Dcore.h352 #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ macro
/linux/arch/xtensa/variants/csp/include/variant/
A Dcore.h351 #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ macro

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