| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_dpp.c | 54 uint32_t alpha_en = 1; in dpp201_cnv_setup() local
75 alpha_en = 0; in dpp201_cnv_setup()
126 alpha_en = 0; in dpp201_cnv_setup()
130 alpha_en = 0; in dpp201_cnv_setup()
146 alpha_en = 0; in dpp201_cnv_setup()
150 alpha_en = 0; in dpp201_cnv_setup()
165 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp201_cnv_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_dpp.c | 105 uint32_t alpha_en = 1; in dpp2_cnv_setup() local
133 alpha_en = 0; in dpp2_cnv_setup()
185 alpha_en = 0; in dpp2_cnv_setup()
189 alpha_en = 0; in dpp2_cnv_setup()
205 alpha_en = 0; in dpp2_cnv_setup()
209 alpha_en = 0; in dpp2_cnv_setup()
224 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp2_cnv_setup()
315 if (scl_data->lb_params.alpha_en in dscl2_calc_lb_num_partitions()
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| A D | dcn20_hwseq.c | 1486 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; in dcn20_update_dchubp_dpp()
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| /linux/drivers/gpu/drm/rockchip/ |
| A D | rockchip_vop_reg.c | 108 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0),
126 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1),
195 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1),
284 .alpha_en = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 0),
300 .alpha_en = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 0),
317 .alpha_en = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 0),
379 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 0),
397 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 1),
412 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 2),
499 .alpha_en = VOP_REG(RK3188_ALPHA_CTRL, 0x1, 0),
[all …]
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| A D | rockchip_drm_vop.h | 183 struct vop_reg alpha_en; member
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| A D | rockchip_drm_vop.c | 1022 VOP_WIN_SET(vop, win, alpha_en, 1); in vop_plane_atomic_update()
1025 VOP_WIN_SET(vop, win, alpha_en, 0); in vop_plane_atomic_update()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_dpp.c | 291 uint32_t alpha_en; in dpp1_cnv_setup() local
302 alpha_en = 1; in dpp1_cnv_setup()
337 alpha_en = 0; in dpp1_cnv_setup()
390 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp1_cnv_setup()
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| A D | dcn10_dpp_dscl.c | 243 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ in dpp1_dscl_set_lb()
249 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ in dpp1_dscl_set_lb()
484 if (scl_data->lb_params.alpha_en in dpp1_dscl_calc_lb_num_partitions()
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| A D | dcn10_hw_sequencer.c | 2598 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; in update_scaler()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | transform.h | 154 bool alpha_en; member
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| /linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| A D | dce60_hw_sequencer.c | 312 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; in dce60_program_front_end_for_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_dpp.c | 181 uint32_t alpha_en = 1; in dpp3_cnv_setup() local
212 alpha_en = 0; in dpp3_cnv_setup()
308 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp3_cnv_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_transform.c | 486 REG_UPDATE(LB_DATA_FORMAT, ALPHA_EN, data->lb_params.alpha_en); in dce_transform_set_scaler()
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| A D | dce110_hw_sequencer.c | 1647 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2785 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 1108 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha; in resource_build_scaling_params()
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