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Searched refs:base_reg (Results 1 – 25 of 54) sorted by relevance

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/linux/drivers/misc/habanalabs/goya/
A Dgoya_coresight.c232 u64 base_reg; in goya_config_stm() local
252 WREG32(base_reg + 0xD64, 7); in goya_config_stm()
305 u64 base_reg; in goya_config_etf() local
340 WREG32(base_reg + 0x20, 0); in goya_config_etf()
352 WREG32(base_reg + 0x20, 1); in goya_config_etf()
354 WREG32(base_reg + 0x34, 0); in goya_config_etf()
355 WREG32(base_reg + 0x28, 0); in goya_config_etf()
482 u64 base_reg; in goya_config_funnel() local
502 u64 base_reg; in goya_config_bmon() local
512 WREG32(base_reg + 0x104, 1); in goya_config_bmon()
[all …]
/linux/arch/sparc/include/asm/
A Dwinmacro.h38 #define LOAD_PT_INS(base_reg) \ argument
44 #define LOAD_PT_GLOBALS(base_reg) \ argument
50 #define LOAD_PT_YREG(base_reg, scratch) \ argument
60 LOAD_PT_YREG(base_reg, scratch) \
61 LOAD_PT_INS(base_reg) \
62 LOAD_PT_GLOBALS(base_reg) \
65 #define STORE_PT_INS(base_reg) \ argument
71 #define STORE_PT_GLOBALS(base_reg) \ argument
77 #define STORE_PT_YREG(base_reg, scratch) \ argument
88 STORE_PT_GLOBALS(base_reg) \
[all …]
/linux/drivers/misc/habanalabs/gaudi/
A Dgaudi_coresight.c393 u64 base_reg; in gaudi_config_stm() local
413 WREG32(base_reg + 0xD64, 7); in gaudi_config_stm()
471 u64 base_reg; in gaudi_config_etf() local
506 WREG32(base_reg + 0x20, 0); in gaudi_config_etf()
518 WREG32(base_reg + 0x20, 1); in gaudi_config_etf()
520 WREG32(base_reg + 0x34, 0); in gaudi_config_etf()
521 WREG32(base_reg + 0x28, 0); in gaudi_config_etf()
688 u64 base_reg; in gaudi_config_funnel() local
708 u64 base_reg; in gaudi_config_bmon() local
717 WREG32(base_reg + 0x104, 1); in gaudi_config_bmon()
[all …]
/linux/drivers/base/regmap/
A Dregcache-rbtree.c27 unsigned int base_reg; member
44 *base = rbnode->base_reg; in regcache_rbtree_get_base_top_reg()
102 unsigned int base_reg; in regcache_rbtree_insert() local
112 base_reg = rbnode->base_reg; in regcache_rbtree_insert()
276 offset = (rbnode->base_reg - base_reg) / map->reg_stride; in regcache_rbtree_insert_to_block()
309 rbnode->base_reg = base_reg; in regcache_rbtree_insert_to_block()
430 if (reg < base_reg) in regcache_rbtree_write()
480 if (base_reg > max) in regcache_rbtree_sync()
485 if (min > base_reg) in regcache_rbtree_sync()
520 if (base_reg > max) in regcache_rbtree_drop()
[all …]
/linux/drivers/crypto/keembay/
A Docs-aes.c219 aes_dev->base_reg + AES_ACTIVE_OFFSET); in aes_a_op_termination()
234 aes_dev->base_reg + AES_ACTIVE_OFFSET); in aes_a_set_last_gcx()
243 aes_active_reg = ioread32(aes_dev->base_reg + in aes_a_wait_last_gcx()
268 aes_dev->base_reg + AES_ACTIVE_OFFSET); in aes_a_set_last_gcx_and_adata()
335 aes_dev->base_reg + AES_A_DMA_MSI_IER_OFFSET); in aes_irq_disable()
507 aes_dev->base_reg + AES_KEY_0_OFFSET + in ocs_aes_set_key()
1042 iowrite8(in_tag[i], aes_dev->base_reg + in ocs_aes_ccm_write_encrypted_tag()
1114 iowrite8(b0[i], aes_dev->base_reg + in ocs_aes_ccm_write_b0()
1155 aes_dev->base_reg + in ocs_aes_ccm_write_adata_len()
1278 tag[i] = ioread32(aes_dev->base_reg + in ccm_compare_tag_to_yr()
[all …]
A Dkeembay-ocs-ecc.c90 void __iomem *base_reg; member
142 return readl_poll_timeout((dev->base_reg + HW_OFFS_OCS_ECC_STATUS), in ocs_ecc_wait_idle()
151 ecc_dev->base_reg + HW_OFFS_OCS_ECC_COMMAND); in ocs_ecc_cmd_start()
164 memcpy_toio(dev->base_reg + HW_OFFS_OCS_ECC_DATA_IN, data_in, in ocs_ecc_write_cmd_and_data()
190 memcpy_fromio(cx_out, dev->base_reg + HW_OFFS_OCS_ECC_CX_DATA_OUT, in ocs_ecc_read_cx_out()
204 memcpy_fromio(cy_out, dev->base_reg + HW_OFFS_OCS_ECC_CY_DATA_OUT, in ocs_ecc_read_cy_out()
874 status = ioread32(ecc_dev->base_reg + HW_OFFS_OCS_ECC_ISR); in ocs_ecc_irq_handler()
875 iowrite32(status, ecc_dev->base_reg + HW_OFFS_OCS_ECC_ISR); in ocs_ecc_irq_handler()
903 ecc_dev->base_reg = devm_platform_ioremap_resource(pdev, 0); in kmb_ocs_ecc_probe()
904 if (IS_ERR(ecc_dev->base_reg)) { in kmb_ocs_ecc_probe()
[all …]
/linux/drivers/gpu/drm/imx/dcss/
A Ddcss-blkctl.c26 void __iomem *base_reg; member
32 dcss_writel(0, blkctl->base_reg + DCSS_BLKCTL_CONTROL0); in dcss_blkctl_cfg()
35 blkctl->base_reg + DCSS_BLKCTL_CONTROL0); in dcss_blkctl_cfg()
38 blkctl->base_reg + DCSS_BLKCTL_RESET_CTRL); in dcss_blkctl_cfg()
49 blkctl->base_reg = ioremap(blkctl_base, SZ_4K); in dcss_blkctl_init()
50 if (!blkctl->base_reg) { in dcss_blkctl_init()
66 if (blkctl->base_reg) in dcss_blkctl_exit()
67 iounmap(blkctl->base_reg); in dcss_blkctl_exit()
A Ddcss-dtg.c80 void __iomem *base_reg; member
101 dcss_writel(val, dtg->base_reg + ofs); in dcss_dtg_write()
134 dtg->base_reg + DCSS_DTG_INT_MASK); in dcss_dtg_irq_config()
163 dtg->base_reg = ioremap(dtg_base, SZ_4K); in dcss_dtg_init()
164 if (!dtg->base_reg) { in dcss_dtg_init()
185 iounmap(dtg->base_reg); in dcss_dtg_init()
197 if (dtg->base_reg) in dcss_dtg_exit()
198 iounmap(dtg->base_reg); in dcss_dtg_exit()
365 dtg->base_reg + DCSS_DTG_INT_CONTROL); in dcss_dtg_vblank_irq_enable()
381 dtg->base_reg + DCSS_DTG_INT_CONTROL); in dcss_dtg_ctxld_kick_irq_enable()
[all …]
A Ddcss-ss.c64 void __iomem *base_reg; member
76 dcss_writel(val, ss->base_reg + ofs); in dcss_ss_write()
94 ss->base_reg = ioremap(ss_base, SZ_4K); in dcss_ss_init()
95 if (!ss->base_reg) { in dcss_ss_init()
110 dcss_writel(0, ss->base_reg + DCSS_SS_SYS_CTRL); in dcss_ss_exit()
112 if (ss->base_reg) in dcss_ss_exit()
113 iounmap(ss->base_reg); in dcss_ss_exit()
178 dcss_writel(0, ss->base_reg + DCSS_SS_SYS_CTRL); in dcss_ss_shutoff()
A Ddcss-dpr.c93 void __iomem *base_reg; member
138 ch->base_reg = ioremap(ch->base_ofs, SZ_4K); in dcss_dpr_ch_init_all()
139 if (!ch->base_reg) { in dcss_dpr_ch_init_all()
148 dcss_writel(0xff, ch->base_reg + DCSS_DPR_IRQ_MASK); in dcss_dpr_ch_init_all()
171 if (dpr->ch[i].base_reg) in dcss_dpr_init()
172 iounmap(dpr->ch[i].base_reg); in dcss_dpr_init()
191 dcss_writel(0, ch->base_reg + DCSS_DPR_SYSTEM_CTRL0); in dcss_dpr_exit()
193 if (ch->base_reg) in dcss_dpr_exit()
194 iounmap(ch->base_reg); in dcss_dpr_exit()
/linux/arch/arm/mach-omap1/
A Dirq.c59 unsigned long base_reg; member
117 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
118 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
119 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
125 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
126 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
129 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
130 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
137 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
138 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
[all …]
/linux/arch/nds32/kernel/
A Dtraps.c64 while (!kstack_end(base_reg)) { in __dump()
65 ret_addr = *base_reg++; in __dump()
75 while (!kstack_end((void *)base_reg) && in __dump()
76 !((unsigned long)base_reg & 0x3) && in __dump()
77 ((unsigned long)base_reg >= TASK_SIZE)) { in __dump()
79 ret_addr = base_reg[LP_OFFSET]; in __dump()
80 next_fp = base_reg[FP_OFFSET]; in __dump()
89 base_reg = (unsigned long *)next_fp; in __dump()
97 unsigned long *base_reg; in show_stack() local
103 base_reg = (unsigned long *)(tsk->thread.cpu_context.sp); in show_stack()
[all …]
/linux/sound/soc/codecs/
A Darizona.h168 #define ARIZONA_MUX_ENUMS(name, base_reg) \ argument
172 #define ARIZONA_MIXER_ENUMS(name, base_reg) \ argument
173 ARIZONA_MUX_ENUMS(name##_in1, base_reg); \
174 ARIZONA_MUX_ENUMS(name##_in2, base_reg + 2); \
175 ARIZONA_MUX_ENUMS(name##_in3, base_reg + 4); \
176 ARIZONA_MUX_ENUMS(name##_in4, base_reg + 6)
178 #define ARIZONA_DSP_AUX_ENUMS(name, base_reg) \ argument
179 ARIZONA_MUX_ENUMS(name##_aux1, base_reg); \
180 ARIZONA_MUX_ENUMS(name##_aux2, base_reg + 8); \
181 ARIZONA_MUX_ENUMS(name##_aux3, base_reg + 16); \
[all …]
A Dmadera.h215 #define MADERA_MUX_ENUMS(name, base_reg) \ argument
219 #define MADERA_MIXER_ENUMS(name, base_reg) \ argument
220 MADERA_MUX_ENUMS(name##_in1, base_reg); \
221 MADERA_MUX_ENUMS(name##_in2, base_reg + 2); \
222 MADERA_MUX_ENUMS(name##_in3, base_reg + 4); \
223 MADERA_MUX_ENUMS(name##_in4, base_reg + 6)
225 #define MADERA_DSP_AUX_ENUMS(name, base_reg) \ argument
226 MADERA_MUX_ENUMS(name##_aux1, base_reg); \
227 MADERA_MUX_ENUMS(name##_aux2, base_reg + 8); \
228 MADERA_MUX_ENUMS(name##_aux3, base_reg + 16); \
[all …]
/linux/drivers/gpu/drm/sun4i/
A Dsun8i_csc.c115 u32 base_reg; in sun8i_csc_set_coefficients() local
122 base_reg = SUN8I_CSC_COEFF(base, 0); in sun8i_csc_set_coefficients()
123 regmap_bulk_write(map, base_reg, table, 12); in sun8i_csc_set_coefficients()
128 base_reg = SUN8I_CSC_COEFF(base, i + 1); in sun8i_csc_set_coefficients()
130 base_reg = SUN8I_CSC_COEFF(base, i - 1); in sun8i_csc_set_coefficients()
132 base_reg = SUN8I_CSC_COEFF(base, i); in sun8i_csc_set_coefficients()
133 regmap_write(map, base_reg, table[i]); in sun8i_csc_set_coefficients()
/linux/drivers/watchdog/
A Drdc321x_wdt.c51 int base_reg; member
67 rdc321x_wdt_device.base_reg, &val); in rdc321x_wdt_trigger()
70 rdc321x_wdt_device.base_reg, val); in rdc321x_wdt_trigger()
99 rdc321x_wdt_device.base_reg, RDC_CLS_TMR); in rdc321x_wdt_start()
103 rdc321x_wdt_device.base_reg, in rdc321x_wdt_start()
159 rdc321x_wdt_device.base_reg, &value); in rdc321x_wdt_ioctl()
233 rdc321x_wdt_device.base_reg = r->start; in rdc321x_wdt_probe()
247 rdc321x_wdt_device.base_reg, RDC_WDT_RST); in rdc321x_wdt_probe()
/linux/drivers/media/dvb-frontends/
A Ddibx000_common.c105 dibx000_read_word(mst, mst->base_reg + 2); in dibx000_master_i2c_write()
112 dibx000_write_word(mst, mst->base_reg, data); in dibx000_master_i2c_write()
129 dibx000_write_word(mst, mst->base_reg+1, da); in dibx000_master_i2c_write()
161 dibx000_write_word(mst, mst->base_reg+1, da); in dibx000_master_i2c_read()
169 da = dibx000_read_word(mst, mst->base_reg); in dibx000_master_i2c_read()
188 return dibx000_write_word(mst, mst->base_reg + 3, (u16)(60000 / speed)); in dibx000_i2c_set_speed()
204 return dibx000_write_word(mst, mst->base_reg + 4, intf); in dibx000_i2c_select_interface()
277 tx[0] = (((mst->base_reg + 1) >> 8) & 0xff); in dibx000_i2c_gate_ctrl()
278 tx[1] = ((mst->base_reg + 1) & 0xff); in dibx000_i2c_gate_ctrl()
458 mst->base_reg = 1024; in dibx000_init_i2c_master()
[all …]
/linux/arch/mips/kernel/
A Dmips-cm.c201 u32 base_reg; in __mips_cm_l2sync_phys_base() local
207 base_reg = read_gcr_l2_only_sync_base(); in __mips_cm_l2sync_phys_base()
208 if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN) in __mips_cm_l2sync_phys_base()
209 return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE; in __mips_cm_l2sync_phys_base()
244 u32 base_reg; in mips_cm_probe() local
264 base_reg = read_gcr_base(); in mips_cm_probe()
265 if ((base_reg & CM_GCR_BASE_GCRBASE) != addr) { in mips_cm_probe()
/linux/sound/soc/cirrus/
A Dep93xx-i2s.c109 unsigned base_reg; in ep93xx_i2s_enable() local
124 base_reg = EP93XX_I2S_TX0EN; in ep93xx_i2s_enable()
126 base_reg = EP93XX_I2S_RX0EN; in ep93xx_i2s_enable()
127 ep93xx_i2s_write_reg(info, base_reg, 1); in ep93xx_i2s_enable()
139 unsigned base_reg; in ep93xx_i2s_disable() local
148 base_reg = EP93XX_I2S_TX0EN; in ep93xx_i2s_disable()
150 base_reg = EP93XX_I2S_RX0EN; in ep93xx_i2s_disable()
151 ep93xx_i2s_write_reg(info, base_reg, 0); in ep93xx_i2s_disable()
/linux/drivers/net/dsa/mv88e6xxx/
A Dglobal2_scratch.c52 int base_reg, unsigned int offset, in mv88e6xxx_g2_scratch_get_bit() argument
55 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_get_bit()
79 int base_reg, unsigned int offset, in mv88e6xxx_g2_scratch_set_bit() argument
82 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_set_bit()
/linux/drivers/input/keyboard/
A Dtm2-touchkey.c39 u8 base_reg; member
59 .base_reg = 0x00,
66 .base_reg = 0x00,
80 .base_reg = 0x00,
108 touchkey->variant->base_reg, data); in tm2_touchkey_led_brightness_set()
/linux/drivers/bus/
A Duniphier-system-bus.c118 void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE; in uniphier_system_bus_check_boot_swap() local
121 is_swapped = !(readl(base_reg) & UNIPHIER_SBC_BASE_BE); in uniphier_system_bus_check_boot_swap()
136 void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE; in uniphier_system_bus_set_reg() local
171 writel(val, base_reg + UNIPHIER_SBC_STRIDE * i); in uniphier_system_bus_set_reg()
/linux/drivers/clk/tegra/
A Dclk-tegra124.c188 .base_reg = PLLX_BASE,
222 .base_reg = PLLC_BASE,
276 .base_reg = PLLC2_BASE,
298 .base_reg = PLLC3_BASE,
357 .base_reg = PLLC4_BASE,
420 .base_reg = PLLM_BASE,
477 .base_reg = PLLE_BASE,
553 .base_reg = PLLP_BASE,
582 .base_reg = PLLA_BASE,
627 .base_reg = PLLD_BASE,
[all …]
A Dclk-tegra210.c1660 .base_reg = PLLX_BASE,
1711 .base_reg = PLLC_BASE,
1750 .base_reg = PLLC2_BASE,
1780 .base_reg = PLLC3_BASE,
1845 .base_reg = PLLC4_BASE,
1899 .base_reg = PLLM_BASE,
1971 .base_reg = PLLE_BASE,
2047 .base_reg = PLLP_BASE,
2120 .base_reg = PLLA_BASE,
2167 .base_reg = PLLD_BASE,
[all …]
A Dclk-tegra114.c184 .base_reg = PLLC_BASE,
235 .base_reg = PLLC2_BASE,
257 .base_reg = PLLC3_BASE,
306 .base_reg = PLLM_BASE,
346 .base_reg = PLLP_BASE,
376 .base_reg = PLLA_BASE,
412 .base_reg = PLLD_BASE,
430 .base_reg = PLLD2_BASE,
472 .base_reg = PLLU_BASE,
501 .base_reg = PLLX_BASE,
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