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Searched refs:clk_name (Results 1 – 25 of 146) sorted by relevance

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/linux/drivers/gpu/drm/msm/dp/
A Ddp_parser.c121 const char *clk_name) in dp_parser_check_prefix() argument
130 const char *clk_name; in dp_parser_init_clk_data() local
144 "clock-names", i, &clk_name); in dp_parser_init_clk_data()
148 if (dp_parser_check_prefix("core", clk_name)) in dp_parser_init_clk_data()
151 if (dp_parser_check_prefix("ctrl", clk_name)) in dp_parser_init_clk_data()
154 if (dp_parser_check_prefix("stream", clk_name)) in dp_parser_init_clk_data()
210 const char *clk_name; in dp_parser_clock() local
230 i, &clk_name); in dp_parser_clock()
239 strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name)); in dp_parser_clock()
246 strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name)); in dp_parser_clock()
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/linux/drivers/clk/zynqmp/
A Dpll.c53 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_get_mode() local
60 __func__, clk_name, ret); in zynqmp_pll_get_mode()
76 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_mode() local
88 __func__, clk_name, ret); in zynqmp_pll_set_mode()
149 __func__, clk_name, ret); in zynqmp_pll_recalc_rate()
201 clk_name); in zynqmp_pll_set_rate()
204 __func__, clk_name, ret); in zynqmp_pll_set_rate()
215 __func__, clk_name, ret); in zynqmp_pll_set_rate()
237 __func__, clk_name, ret); in zynqmp_pll_is_enabled()
269 __func__, clk_name, ret); in zynqmp_pll_enable()
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A Dclk-gate-zynqmp.c37 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_enable() local
45 __func__, clk_name, ret); in zynqmp_clk_gate_enable()
57 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_disable() local
65 __func__, clk_name, ret); in zynqmp_clk_gate_disable()
77 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_is_enabled() local
84 __func__, clk_name, ret); in zynqmp_clk_gate_is_enabled()
A Dclkc.c71 char clk_name[MAX_NAME_LEN]; member
160 static int zynqmp_get_clock_name(u32 clk_id, char *clk_name) in zynqmp_get_clock_name() argument
166 strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN); in zynqmp_get_clock_name()
601 clk_out[j] = kasprintf(GFP_KERNEL, "%s%s", clk_name, in zynqmp_register_clk_topology()
604 clk_out[j] = kasprintf(GFP_KERNEL, "%s", clk_name); in zynqmp_register_clk_topology()
616 __func__, clk_dev_id, clk_name, in zynqmp_register_clk_topology()
641 char clk_name[MAX_NAME_LEN]; in zynqmp_register_clocks() local
644 if (zynqmp_get_clock_name(i, clk_name)) in zynqmp_register_clocks()
658 clock[i].clk_name); in zynqmp_register_clocks()
663 zynqmp_register_clk_topology(i, clk_name, in zynqmp_register_clocks()
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A Ddivider.c83 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_recalc_rate() local
93 __func__, clk_name, ret); in zynqmp_clk_divider_recalc_rate()
106 clk_name); in zynqmp_clk_divider_recalc_rate()
169 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_round_rate() local
181 __func__, clk_name, ret); in zynqmp_clk_divider_round_rate()
226 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_set_rate() local
248 __func__, clk_name, ret); in zynqmp_clk_divider_set_rate()
/linux/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_io_util.c32 clk_arry[i].clk = clk_get(dev, clk_arry[i].clk_name); in msm_dss_get_clk()
37 clk_arry[i].clk_name, rc); in msm_dss_get_clk()
63 clk_arry[i].clk_name, in msm_dss_clk_set_rate()
71 clk_arry[i].clk_name, rc); in msm_dss_clk_set_rate()
78 clk_arry[i].clk_name); in msm_dss_clk_set_rate()
95 clk_arry[i].clk_name); in msm_dss_enable_clk()
101 clk_arry[i].clk_name, rc); in msm_dss_enable_clk()
113 clk_arry[i].clk_name); in msm_dss_enable_clk()
154 strlcpy(mp->clk_config[i].clk_name, clock_name, in msm_dss_parse_clock()
155 sizeof(mp->clk_config[i].clk_name)); in msm_dss_parse_clock()
/linux/drivers/clk/sunxi/
A Dclk-a10-pll2.c41 const char *clk_name = node->name, *parent; in sun4i_pll2_setup() local
121 SUN4I_A10_PLL2_1X, &clk_name); in sun4i_pll2_setup()
122 clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
136 SUN4I_A10_PLL2_2X, &clk_name); in sun4i_pll2_setup()
137 clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
145 SUN4I_A10_PLL2_4X, &clk_name); in sun4i_pll2_setup()
146 clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
154 SUN4I_A10_PLL2_8X, &clk_name); in sun4i_pll2_setup()
155 clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
A Dclk-sun4i-pll3.c23 const char *clk_name = node->name, *parent; in sun4i_a10_pll3_setup() local
31 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_pll3_setup()
36 pr_err("%s: Could not map the clock registers\n", clk_name); in sun4i_a10_pll3_setup()
57 clk = clk_register_composite(NULL, clk_name, in sun4i_a10_pll3_setup()
64 pr_err("%s: Couldn't register the clock\n", clk_name); in sun4i_a10_pll3_setup()
71 clk_name); in sun4i_a10_pll3_setup()
A Dclk-sunxi.c655 const char *clk_name = node->name; in sunxi_mux_clk_setup() local
680 clk_name, PTR_ERR(clk)); in sunxi_mux_clk_setup()
686 __func__, clk_name); in sunxi_mux_clk_setup()
809 __func__, clk_name); in sunxi_divider_clk_setup()
948 const char *clk_name; in sunxi_divs_clk_setup() local
978 0, &clk_name); in sunxi_divs_clk_setup()
979 endp = strchr(clk_name, '_'); in sunxi_divs_clk_setup()
981 derived_name = kstrndup(clk_name, endp - clk_name, in sunxi_divs_clk_setup()
987 factors.name = clk_name; in sunxi_divs_clk_setup()
1021 i, &clk_name) != 0) in sunxi_divs_clk_setup()
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A Dclk-sun4i-display.c105 const char *clk_name = node->name; in sun4i_a10_display_init() local
115 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_display_init()
119 pr_err("%s: Could not map the clock registers\n", clk_name); in sun4i_a10_display_init()
125 pr_err("%s: Could not retrieve the parents\n", clk_name); in sun4i_a10_display_init()
157 clk = clk_register_composite(NULL, clk_name, in sun4i_a10_display_init()
165 pr_err("%s: Couldn't register the clock\n", clk_name); in sun4i_a10_display_init()
171 pr_err("%s: Couldn't register DT provider\n", clk_name); in sun4i_a10_display_init()
198 clk_name); in sun4i_a10_display_init()
A Dclk-sun4i-tcon-ch1.c227 const char *clk_name = node->name; in tcon_ch1_setup() local
235 of_property_read_string(node, "clock-output-names", &clk_name); in tcon_ch1_setup()
239 pr_err("%s: Could not map the clock registers\n", clk_name); in tcon_ch1_setup()
245 pr_err("%s Could not retrieve the parents\n", clk_name); in tcon_ch1_setup()
253 init.name = clk_name; in tcon_ch1_setup()
265 pr_err("%s: Couldn't register the clock\n", clk_name); in tcon_ch1_setup()
271 pr_err("%s: Couldn't register our clock provider\n", clk_name); in tcon_ch1_setup()
A Dclk-a10-codec.c17 const char *clk_name = node->name, *parent_name; in sun4i_codec_clk_setup() local
24 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_codec_clk_setup()
27 clk = clk_register_gate(NULL, clk_name, parent_name, in sun4i_codec_clk_setup()
/linux/drivers/mailbox/
A Dqcom-apcs-ipc-mailbox.c29 char *clk_name; member
33 .offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
37 .offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
41 .offset = 8, .clk_name = NULL
45 .offset = 16, .clk_name = NULL
49 .offset = 12, .clk_name = NULL
53 .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
118 if (apcs_data->clk_name) { in qcom_apcs_ipc_probe()
120 apcs_data->clk_name, in qcom_apcs_ipc_probe()
/linux/drivers/clk/pxa/
A Dclk-pxa.h19 #define MUX_RO_RATE_RO_OPS(name, clk_name) \ argument
31 return clk_register_composite(NULL, clk_name, \
39 #define RATE_RO_OPS(name, clk_name) \ argument
46 return clk_register_composite(NULL, clk_name, \
54 #define RATE_OPS(name, clk_name) \ argument
63 return clk_register_composite(NULL, clk_name, \
71 #define MUX_OPS(name, clk_name, flags) \ argument
80 return clk_register_composite(NULL, clk_name, \
/linux/drivers/clk/h8300/
A Dclk-div.c20 const char *clk_name = node->name; in h8300_div_clk_setup() local
28 pr_err("%s: no parent found\n", clk_name); in h8300_div_clk_setup()
34 pr_err("%s: failed to map divide register\n", clk_name); in h8300_div_clk_setup()
43 hw = clk_hw_register_divider(NULL, clk_name, parent_name, in h8300_div_clk_setup()
51 __func__, clk_name, PTR_ERR(hw)); in h8300_div_clk_setup()
A Dclk-h8s2678.c89 const char *clk_name = node->name; in h8s2678_pll_clk_setup() local
97 pr_err("%s: no parent found\n", clk_name); in h8s2678_pll_clk_setup()
108 pr_err("%s: failed to map divide register\n", clk_name); in h8s2678_pll_clk_setup()
114 pr_err("%s: failed to map multiply register\n", clk_name); in h8s2678_pll_clk_setup()
119 init.name = clk_name; in h8s2678_pll_clk_setup()
129 __func__, clk_name, ret); in h8s2678_pll_clk_setup()
/linux/drivers/clk/mvebu/
A Dclk-cpu.c36 const char *clk_name; member
198 char *clk_name = kzalloc(5, GFP_KERNEL); in of_cpu_clk_setup() local
201 if (WARN_ON(!clk_name)) in of_cpu_clk_setup()
208 sprintf(clk_name, "cpu%d", cpu); in of_cpu_clk_setup()
211 cpuclk[cpu].clk_name = clk_name; in of_cpu_clk_setup()
218 init.name = cpuclk[cpu].clk_name; in of_cpu_clk_setup()
237 kfree(cpuclk[ncpus].clk_name); in of_cpu_clk_setup()
/linux/drivers/clk/
A Dclk-nspire.c69 const char *clk_name = node->name; in nspire_ahbdiv_setup() local
81 of_property_read_string(node, "clock-output-names", &clk_name); in nspire_ahbdiv_setup()
84 hw = clk_hw_register_fixed_factor(NULL, clk_name, parent_name, 0, in nspire_ahbdiv_setup()
111 const char *clk_name = node->name; in nspire_clk_setup() local
122 of_property_read_string(node, "clock-output-names", &clk_name); in nspire_clk_setup()
124 hw = clk_hw_register_fixed_rate(NULL, clk_name, NULL, 0, in nspire_clk_setup()
A Dclk-xgene.c171 const char *clk_name = np->full_name; in xgene_pllclk_init() local
183 clk_name, of_clk_get_parent_name(np, 0), in xgene_pllclk_init()
188 clk_register_clkdev(clk, clk_name, NULL); in xgene_pllclk_init()
189 pr_debug("Add %s clock PLL\n", clk_name); in xgene_pllclk_init()
379 const char *clk_name = np->full_name; in xgene_pmdclk_init() local
407 clk = xgene_register_clk_pmd(NULL, clk_name, in xgene_pmdclk_init()
414 clk_register_clkdev(clk, clk_name, NULL); in xgene_pmdclk_init()
415 pr_debug("Add %s clock\n", clk_name); in xgene_pmdclk_init()
667 const char *clk_name = np->full_name; in xgene_devclk_init() local
721 clk = xgene_register_clk(NULL, clk_name, in xgene_devclk_init()
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/linux/drivers/clk/keystone/
A Dpll.c254 const char *clk_name = node->name; in of_pll_div_clk_init() local
256 of_property_read_string(node, "clock-output-names", &clk_name); in of_pll_div_clk_init()
282 clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift, in of_pll_div_clk_init()
287 pr_err("%s: error registering divider %s\n", __func__, clk_name); in of_pll_div_clk_init()
303 const char *clk_name = node->name; in of_pll_mux_clk_init() local
305 of_property_read_string(node, "clock-output-names", &clk_name); in of_pll_mux_clk_init()
328 clk = clk_register_mux(NULL, clk_name, (const char **)&parents, in of_pll_mux_clk_init()
334 pr_err("%s: error registering mux %s\n", __func__, clk_name); in of_pll_mux_clk_init()
/linux/tools/testing/selftests/kvm/x86_64/
A Dkvm_clock_test.c147 char *clk_name; in check_clocksource() local
164 clk_name = malloc(st.st_size); in check_clocksource()
165 TEST_ASSERT(clk_name, "failed to allocate buffer to read file\n"); in check_clocksource()
167 if (!fgets(clk_name, st.st_size, fp)) { in check_clocksource()
173 TEST_ASSERT(!strncmp(clk_name, "tsc\n", st.st_size), in check_clocksource()
174 "clocksource not supported: %s", clk_name); in check_clocksource()
/linux/drivers/iio/adc/
A Daspeed_adc.c487 char clk_name[32], clk_parent_name[32]; in aspeed_adc_probe() local
506 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-fixed-div", in aspeed_adc_probe()
509 &pdev->dev, clk_name, clk_parent_name, 0, 1, 2); in aspeed_adc_probe()
518 snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), clk_name); in aspeed_adc_probe()
521 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-prescaler", in aspeed_adc_probe()
524 &pdev->dev, clk_name, clk_parent_name, 0, in aspeed_adc_probe()
530 clk_name); in aspeed_adc_probe()
537 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-scaler", in aspeed_adc_probe()
540 &pdev->dev, clk_name, clk_parent_name, scaler_flags, in aspeed_adc_probe()
/linux/drivers/gpu/drm/msm/dsi/phy/
A Ddsi_phy_10nm.c562 char clk_name[32], parent[32], vco_name[32]; in pll_10nm_register() local
584 snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id); in pll_10nm_register()
587 hw = devm_clk_hw_register_divider(dev, clk_name, in pll_10nm_register()
597 snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id); in pll_10nm_register()
601 hw = devm_clk_hw_register_divider(dev, clk_name, parent, in pll_10nm_register()
616 hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, in pll_10nm_register()
628 hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, in pll_10nm_register()
638 hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, in pll_10nm_register()
645 snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->phy->id); in pll_10nm_register()
651 hw = devm_clk_hw_register_mux(dev, clk_name, in pll_10nm_register()
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/linux/drivers/clk/ti/
A Dclockdomain.c110 const char *clk_name; in omap2_init_clk_clkdm() local
115 clk_name = __clk_get_name(hw->clk); in omap2_init_clk_clkdm()
120 clk_name, clk->clkdm_name); in omap2_init_clk_clkdm()
124 clk_name, clk->clkdm_name); in omap2_init_clk_clkdm()
/linux/drivers/staging/clocking-wizard/
A Dclk-xlnx-clock-wizard.c418 const char *clk_name; in clk_wzrd_probe() local
476 clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev)); in clk_wzrd_probe()
477 if (!clk_name) { in clk_wzrd_probe()
491 (&pdev->dev, clk_name, in clk_wzrd_probe()
500 clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev)); in clk_wzrd_probe()
501 if (!clk_name) { in clk_wzrd_probe()
509 (&pdev->dev, clk_name, in clk_wzrd_probe()
532 clk_name, flags, in clk_wzrd_probe()
541 clk_name, 0, in clk_wzrd_probe()
559 kfree(clk_name); in clk_wzrd_probe()
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