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Searched refs:cntval_mask (Results 1 – 9 of 9) sorted by relevance

/linux/arch/x86/events/zhaoxin/
A Dcore.c535 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in zhaoxin_pmu_init()
546 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; in zhaoxin_pmu_init()
/linux/arch/x86/events/intel/
A Dp6.c226 .cntval_mask = (1ULL << 32) - 1,
A Dknc.c308 .cntval_mask = (1ULL << 40) - 1,
A Dp4.c1333 .cntval_mask = ARCH_P4_CNTRVAL_MASK,
A Dds.c1244 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; in intel_pmu_pebs_enable()
A Dcore.c5612 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in intel_pmu_init()
6364 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; in intel_pmu_init()
/linux/arch/x86/events/amd/
A Dcore.c924 .cntval_mask = (1ULL << 48) - 1,
/linux/arch/x86/events/
A Dcore.c1409 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); in x86_perf_event_set_period()
1425 (u64)(-left) & x86_pmu.cntval_mask); in x86_perf_event_set_period()
2046 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); in x86_pmu_show_pmu_cap()
A Dperf_event.h745 u64 cntval_mask; member

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