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Searched refs:cp_int_cntl (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v6_0.c3240 u32 cp_int_cntl; in gfx_v6_0_set_gfx_eop_interrupt_state() local
3244 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3246 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3251 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3262 u32 cp_int_cntl; in gfx_v6_0_set_compute_eop_interrupt_state() local
3303 u32 cp_int_cntl; in gfx_v6_0_set_priv_reg_fault_state() local
3309 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_reg_fault_state()
3314 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_reg_fault_state()
3328 u32 cp_int_cntl; in gfx_v6_0_set_priv_inst_fault_state() local
3334 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_inst_fault_state()
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A Dgfx_v7_0.c4734 u32 cp_int_cntl; in gfx_v7_0_set_gfx_eop_interrupt_state() local
4738 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4740 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4743 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4745 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4808 u32 cp_int_cntl; in gfx_v7_0_set_priv_reg_fault_state() local
4814 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_reg_fault_state()
4819 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_reg_fault_state()
4833 u32 cp_int_cntl; in gfx_v7_0_set_priv_inst_fault_state() local
4839 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_inst_fault_state()
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A Dgfx_v10_0.c9004 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v10_0_set_gfx_eop_interrupt_state() local
9025 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state()
9026 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
9028 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
9031 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state()
9032 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
9034 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
/linux/drivers/gpu/drm/radeon/
A Dni.h32 int ring, u32 cp_int_cntl);
A Devergreen.c4495 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in evergreen_irq_set() local
4526 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4539 cp_int_cntl |= RB_INT_ENABLE; in evergreen_irq_set()
4540 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4563 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); in evergreen_irq_set()
4567 WREG32(CP_INT_CNTL, cp_int_cntl); in evergreen_irq_set()
A Dni.c1380 int ring, u32 cp_int_cntl) in cayman_cp_int_cntl_setup() argument
1383 WREG32(CP_INT_CNTL, cp_int_cntl); in cayman_cp_int_cntl_setup()
A Dr600.c3763 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in r600_irq_set() local
3821 cp_int_cntl |= RB_INT_ENABLE; in r600_irq_set()
3822 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
3873 WREG32(CP_INT_CNTL, cp_int_cntl); in r600_irq_set()
A Dsi.c6048 u32 cp_int_cntl; in si_irq_set() local
6066 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set()
6078 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6098 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
A Dcik.c7017 u32 cp_int_cntl; in cik_irq_set() local
7037 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set()
7039 cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE; in cik_irq_set()
7063 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7217 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()

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