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Searched refs:csr_base_addr (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/crypto/qat/qat_common/
A Dadf_gen4_hw_data.h27 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
28 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
31 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
32 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
35 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
36 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
39 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
44 void __iomem *_csr_base_addr = csr_base_addr; \
60 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
67 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ argument
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A Dadf_gen4_hw_data.c13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
35 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
47 WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr); in write_csr_ring_base()
53 WRITE_CSR_INT_FLAG(csr_base_addr, bank, value); in write_csr_int_flag()
58 WRITE_CSR_INT_SRCSEL(csr_base_addr, bank); in write_csr_int_srcsel()
63 WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value); in write_csr_int_col_en()
69 WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value); in write_csr_int_col_ctl()
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A Dadf_gen2_hw_data.h30 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
31 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
33 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
34 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
36 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
37 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
40 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
59 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ argument
62 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ argument
69 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ argument
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A Dadf_gen2_hw_data.c163 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
169 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
174 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
180 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
185 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
197 WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr); in write_csr_ring_base()
202 WRITE_CSR_INT_FLAG(csr_base_addr, bank, value); in write_csr_int_flag()
207 WRITE_CSR_INT_SRCSEL(csr_base_addr, bank); in write_csr_int_srcsel()
213 WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value); in write_csr_int_col_en()
219 WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value); in write_csr_int_col_ctl()
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A Dadf_accel_devices.h119 u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
121 void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
123 u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
125 void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
127 u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
128 void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
130 void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
132 void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,
134 void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
135 void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,
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