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Searched refs:cu_info (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/amd/amdkfd/
A Dkfd_mqd_manager.c100 struct kfd_cu_info cu_info; in mqd_symmetrically_map_cu_mask() local
103 amdgpu_amdkfd_get_cu_info(mm->dev->kgd, &cu_info); in mqd_symmetrically_map_cu_mask()
105 if (cu_mask_count > cu_info.cu_active_number) in mqd_symmetrically_map_cu_mask()
106 cu_mask_count = cu_info.cu_active_number; in mqd_symmetrically_map_cu_mask()
112 if (cu_info.num_shader_engines > KFD_MAX_NUM_SE) { in mqd_symmetrically_map_cu_mask()
118 cu_info.num_shader_arrays_per_engine * cu_info.num_shader_engines); in mqd_symmetrically_map_cu_mask()
131 for (se = 0; se < cu_info.num_shader_engines; se++) in mqd_symmetrically_map_cu_mask()
132 for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) in mqd_symmetrically_map_cu_mask()
158 for (i = 0; i < cu_info.num_shader_engines; i++) in mqd_symmetrically_map_cu_mask()
163 for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) { in mqd_symmetrically_map_cu_mask()
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A Dkfd_crat.c1199 struct kfd_cu_info *cu_info, in fill_in_l1_pcache() argument
1253 struct kfd_cu_info *cu_info, in fill_in_l2_l3_pcache() argument
1329 struct kfd_cu_info *cu_info, in kfd_fill_gpu_cache_info() argument
1465 cu_info, in kfd_fill_gpu_cache_info()
1484 cu_info->num_cu_per_sh) ? in kfd_fill_gpu_cache_info()
1486 (cu_info->num_cu_per_sh - k); in kfd_fill_gpu_cache_info()
1494 cu_info, in kfd_fill_gpu_cache_info()
2071 struct kfd_cu_info cu_info; in kfd_create_vcrat_image_gpu() local
2119 cu->num_simd_cores = cu_info.simd_per_cu * cu_info.cu_active_number; in kfd_create_vcrat_image_gpu()
2124 cu_info.num_shader_engines; in kfd_create_vcrat_image_gpu()
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A Dkfd_topology.c1283 struct kfd_cu_info cu_info; in kfd_topology_add_device() local
1375 amdgpu_amdkfd_get_cu_info(dev->gpu->kgd, &cu_info); in kfd_topology_add_device()
1381 cu_info.num_shader_arrays_per_engine; in kfd_topology_add_device()
1474 cu_info.simd_per_cu * cu_info.cu_active_number; in kfd_topology_add_device()
/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_amdkfd.c456 struct amdgpu_cu_info acu_info = adev->gfx.cu_info; in amdgpu_amdkfd_get_cu_info()
458 memset(cu_info, 0, sizeof(*cu_info)); in amdgpu_amdkfd_get_cu_info()
459 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap)) in amdgpu_amdkfd_get_cu_info()
462 cu_info->cu_active_number = acu_info.number; in amdgpu_amdkfd_get_cu_info()
463 cu_info->cu_ao_mask = acu_info.ao_cu_mask; in amdgpu_amdkfd_get_cu_info()
464 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0], in amdgpu_amdkfd_get_cu_info()
468 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; in amdgpu_amdkfd_get_cu_info()
469 cu_info->simd_per_cu = acu_info.simd_per_cu; in amdgpu_amdkfd_get_cu_info()
470 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd; in amdgpu_amdkfd_get_cu_info()
471 cu_info->wave_front_size = acu_info.wave_front_size; in amdgpu_amdkfd_get_cu_info()
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A Damdgpu_atomfirmware.c655 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size); in amdgpu_atomfirmware_get_gfx_info()
656 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd); in amdgpu_atomfirmware_get_gfx_info()
657 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu; in amdgpu_atomfirmware_get_gfx_info()
658 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size); in amdgpu_atomfirmware_get_gfx_info()
671 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size); in amdgpu_atomfirmware_get_gfx_info()
672 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd); in amdgpu_atomfirmware_get_gfx_info()
673 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu; in amdgpu_atomfirmware_get_gfx_info()
674 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size); in amdgpu_atomfirmware_get_gfx_info()
A Dgfx_v9_4_2.c522 adev->gfx.cu_info.number, in gfx_v9_4_2_do_sgprs_init()
532 adev->gfx.cu_info.number * SIMD_ID_MAX * 2, in gfx_v9_4_2_do_sgprs_init()
547 adev->gfx.cu_info.number * 2, in gfx_v9_4_2_do_sgprs_init()
556 pattern[1], adev->gfx.cu_info.number * SIMD_ID_MAX * 6, in gfx_v9_4_2_do_sgprs_init()
587 adev->gfx.cu_info.number, in gfx_v9_4_2_do_sgprs_init()
597 adev->gfx.cu_info.number * SIMD_ID_MAX * 4, in gfx_v9_4_2_do_sgprs_init()
665 adev->gfx.cu_info.number, in gfx_v9_4_2_do_vgprs_init()
682 adev->gfx.cu_info.number * SIMD_ID_MAX, in gfx_v9_4_2_do_vgprs_init()
1839 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v9_4_2_log_cu_timeout_status() local
1851 simd = i / cu_info->max_waves_per_simd; in gfx_v9_4_2_log_cu_timeout_status()
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A Damdgpu_discovery.c560 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); in amdgpu_discovery_get_gfx_info()
561 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); in amdgpu_discovery_get_gfx_info()
562 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); in amdgpu_discovery_get_gfx_info()
563 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); in amdgpu_discovery_get_gfx_info()
579 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); in amdgpu_discovery_get_gfx_info()
580 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); in amdgpu_discovery_get_gfx_info()
581 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); in amdgpu_discovery_get_gfx_info()
582 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); in amdgpu_discovery_get_gfx_info()
A Damdgpu_kms.c857 dev_info->cu_active_number = adev->gfx.cu_info.number; in amdgpu_info_ioctl()
858 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; in amdgpu_info_ioctl()
860 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], in amdgpu_info_ioctl()
861 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); in amdgpu_info_ioctl()
862 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], in amdgpu_info_ioctl()
863 sizeof(adev->gfx.cu_info.bitmap)); in amdgpu_info_ioctl()
869 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; in amdgpu_info_ioctl()
A Dgfx_v7_0.c5169 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v7_0_get_cu_info() local
5178 memset(cu_info, 0, sizeof(*cu_info)); in gfx_v7_0_get_cu_info()
5193 cu_info->bitmap[i][j] = bitmap; in gfx_v7_0_get_cu_info()
5206 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; in gfx_v7_0_get_cu_info()
5212 cu_info->number = active_cu_number; in gfx_v7_0_get_cu_info()
5213 cu_info->ao_cu_mask = ao_cu_mask; in gfx_v7_0_get_cu_info()
5214 cu_info->simd_per_cu = NUM_SIMD_PER_CU; in gfx_v7_0_get_cu_info()
5215 cu_info->max_waves_per_simd = 10; in gfx_v7_0_get_cu_info()
5216 cu_info->max_scratch_slots_per_cu = 32; in gfx_v7_0_get_cu_info()
5217 cu_info->wave_front_size = 64; in gfx_v7_0_get_cu_info()
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A Dgfx_v6_0.c2784 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); in gfx_v6_0_init_ao_cu_mask()
2788 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); in gfx_v6_0_init_ao_cu_mask()
3594 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v6_0_get_cu_info() local
3603 memset(cu_info, 0, sizeof(*cu_info)); in gfx_v6_0_get_cu_info()
3618 cu_info->bitmap[i][j] = bitmap; in gfx_v6_0_get_cu_info()
3631 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; in gfx_v6_0_get_cu_info()
3638 cu_info->number = active_cu_number; in gfx_v6_0_get_cu_info()
3639 cu_info->ao_cu_mask = ao_cu_mask; in gfx_v6_0_get_cu_info()
A Damdgpu_amdkfd_gfx_v9.c881 *max_waves_per_cu = adev->gfx.cu_info.simd_per_cu * in kgd_gfx_v9_get_cu_occupancy()
882 adev->gfx.cu_info.max_waves_per_simd; in kgd_gfx_v9_get_cu_occupancy()
A Damdgpu_amdkfd.h216 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info);
A Damdgpu_gfx.h321 struct amdgpu_cu_info cu_info; member
A Dgfx_v8_0.c7141 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v8_0_get_cu_info() local
7145 memset(cu_info, 0, sizeof(*cu_info)); in gfx_v8_0_get_cu_info()
7165 cu_info->bitmap[i][j] = bitmap; in gfx_v8_0_get_cu_info()
7178 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; in gfx_v8_0_get_cu_info()
7184 cu_info->number = active_cu_number; in gfx_v8_0_get_cu_info()
7185 cu_info->ao_cu_mask = ao_cu_mask; in gfx_v8_0_get_cu_info()
7186 cu_info->simd_per_cu = NUM_SIMD_PER_CU; in gfx_v8_0_get_cu_info()
7187 cu_info->max_waves_per_simd = 10; in gfx_v8_0_get_cu_info()
7188 cu_info->max_scratch_slots_per_cu = 32; in gfx_v8_0_get_cu_info()
7189 cu_info->wave_front_size = 64; in gfx_v8_0_get_cu_info()
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A Dgfx_v9_0.c821 struct amdgpu_cu_info *cu_info);
1798 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v9_0_init_always_on_cu_mask() local
1820 if (cu_info->bitmap[i][j] & mask) { in gfx_v9_0_init_always_on_cu_mask()
1833 cu_info->ao_cu_bitmap[i][j] = cu_bitmap; in gfx_v9_0_init_always_on_cu_mask()
2635 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); in gfx_v9_0_constants_init()
7174 struct amdgpu_cu_info *cu_info) in gfx_v9_0_get_cu_info() argument
7180 if (!adev || !cu_info) in gfx_v9_0_get_cu_info()
7217 cu_info->bitmap[i % 4][j + i / 4] = bitmap; in gfx_v9_0_get_cu_info()
7236 cu_info->number = active_cu_number; in gfx_v9_0_get_cu_info()
7237 cu_info->ao_cu_mask = ao_cu_mask; in gfx_v9_0_get_cu_info()
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A Damdgpu_device.c2022 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); in amdgpu_device_parse_gpu_info_fw()
2023 adev->gfx.cu_info.max_waves_per_simd = in amdgpu_device_parse_gpu_info_fw()
2025 adev->gfx.cu_info.max_scratch_slots_per_cu = in amdgpu_device_parse_gpu_info_fw()
2027 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); in amdgpu_device_parse_gpu_info_fw()
3682 adev->gfx.cu_info.number); in amdgpu_device_init()
A Dgfx_v10_0.c3574 struct amdgpu_cu_info *cu_info);
5251 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); in gfx_v10_0_constants_init()
9621 struct amdgpu_cu_info *cu_info) in gfx_v10_0_get_cu_info() argument
9627 if (!adev || !cu_info) in gfx_v10_0_get_cu_info()
9648 cu_info->bitmap[i][j] = bitmap; in gfx_v10_0_get_cu_info()
9661 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; in gfx_v10_0_get_cu_info()
9667 cu_info->number = active_cu_number; in gfx_v10_0_get_cu_info()
9668 cu_info->ao_cu_mask = ao_cu_mask; in gfx_v10_0_get_cu_info()
9669 cu_info->simd_per_cu = NUM_SIMD_PER_CU; in gfx_v10_0_get_cu_info()
/linux/drivers/net/ethernet/marvell/prestera/
A Dprestera_main.c772 struct netdev_notifier_changeupper_info *cu_info; in prestera_netdev_port_event() local
778 cu_info = container_of(info, in prestera_netdev_port_event()
784 upper = cu_info->upper_dev; in prestera_netdev_port_event()
791 if (!cu_info->linking) in prestera_netdev_port_event()
800 !prestera_lag_master_check(upper, cu_info->upper_info, extack)) in prestera_netdev_port_event()
816 upper = cu_info->upper_dev; in prestera_netdev_port_event()
818 if (cu_info->linking) in prestera_netdev_port_event()
824 if (cu_info->linking) in prestera_netdev_port_event()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu7_clockpowergating.c431 adev->gfx.cu_info.number, in smu7_powergate_gfx()
A Dvega12_hwmgr.c431 data->total_active_cus = adev->gfx.cu_info.number; in vega12_hwmgr_backend_init()
A Dvega20_hwmgr.c473 data->total_active_cus = adev->gfx.cu_info.number; in vega20_hwmgr_backend_init()
A Dvega10_hwmgr.c915 data->total_active_cus = adev->gfx.cu_info.number; in vega10_hwmgr_backend_init()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dvangogh_ppt.c2009 uint32_t req_active_wgps = adev->gfx.cu_info.number/2; in vangogh_post_smu_init()
2027 if (total_cu == adev->gfx.cu_info.number) in vangogh_post_smu_init()
/linux/drivers/net/ethernet/mellanox/mlxsw/
A Dspectrum.c4640 struct netdev_notifier_changeupper_info *cu_info; in mlxsw_sp_netdevice_vxlan_event() local
4649 cu_info = container_of(info, in mlxsw_sp_netdevice_vxlan_event()
4652 upper_dev = cu_info->upper_dev; in mlxsw_sp_netdevice_vxlan_event()
4659 if (cu_info->linking) { in mlxsw_sp_netdevice_vxlan_event()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Dvegam_smumgr.c1912 adev->gfx.cu_info.number, in vegam_enable_reconfig_cus()

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