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/linux/drivers/clk/renesas/
A Drcar-cpg-lib.c89 const struct sd_div_table *div_table; member
135 clock->div_table[clock->cur_div_idx].val & in cpg_sd_clock_enable()
161 clock->div_table[clock->cur_div_idx].div); in cpg_sd_clock_recalc_rate()
174 clock->div_table[i].div); in cpg_sd_clock_determine_rate()
201 clock->div_table[i].div)) in cpg_sd_clock_set_rate()
210 clock->div_table[i].val & in cpg_sd_clock_set_rate()
246 clock->div_table = cpg_sd_div_table; in cpg_sd_clk_register()
250 clock->div_table++; in cpg_sd_clk_register()
255 val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK); in cpg_sd_clk_register()
A Dr9a06g032-clocks.c44 u16 div_table[4]; member
83 .div_table = { __VA_ARGS__ } }
699 i < ARRAY_SIZE(desc->div_table) && desc->div_table[i]; i++) { in r9a06g032_register_div()
700 div->table[div->table_size++] = desc->div_table[i]; in r9a06g032_register_div()
/linux/drivers/clk/ti/
A Ddivider.c343 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, in ti_clk_parse_divider_data() argument
351 if (!div_table) { in ti_clk_parse_divider_data()
361 if (div_table[i] == -1) in ti_clk_parse_divider_data()
363 if (div_table[i]) in ti_clk_parse_divider_data()
377 if (div_table[i] > 0) { in ti_clk_parse_divider_data()
378 tmp[valid_div].div = div_table[i]; in ti_clk_parse_divider_data()
381 if (div_table[i] > max_div) in ti_clk_parse_divider_data()
382 max_div = div_table[i]; in ti_clk_parse_divider_data()
383 if (!min_div || div_table[i] < min_div) in ti_clk_parse_divider_data()
384 min_div = div_table[i]; in ti_clk_parse_divider_data()
A Dclock.h224 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
/linux/drivers/clk/mediatek/
A Dclk-pll.c165 const struct mtk_pll_div_table *div_table = pll->data->div_table; in mtk_pll_calc_values() local
173 if (div_table) { in mtk_pll_calc_values()
174 if (freq > div_table[0].freq) in mtk_pll_calc_values()
175 freq = div_table[0].freq; in mtk_pll_calc_values()
177 for (val = 0; div_table[val + 1].freq != 0; val++) { in mtk_pll_calc_values()
178 if (freq > div_table[val + 1].freq) in mtk_pll_calc_values()
A Dclk-mtk.h236 const struct mtk_pll_div_table *div_table; member
A Dclk-mt7629.c41 .div_table = _div_table, \
A Dclk-mt6797.c626 .div_table = _div_table, \
A Dclk-mt7622.c41 .div_table = _div_table, \
A Dclk-mt8516.c753 .div_table = _div_table, \
A Dclk-mt6779.c1169 .div_table = _div_table, \
/linux/drivers/clk/ingenic/
A Dcgu.c399 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
400 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
420 && clk_info->div.div_table[i]; i++) { in ingenic_clk_calc_hw_div()
421 if (clk_info->div.div_table[i] >= div && in ingenic_clk_calc_hw_div()
422 clk_info->div.div_table[i] < best) { in ingenic_clk_calc_hw_div()
423 best = clk_info->div.div_table[i]; in ingenic_clk_calc_hw_div()
449 if (clk_info->div.div_table) { in ingenic_clk_calc_div()
452 return clk_info->div.div_table[hw_div]; in ingenic_clk_calc_div()
517 if (clk_info->div.div_table) in ingenic_clk_set_rate()
A Dcgu.h102 const u8 *div_table; member
/linux/drivers/clk/mmp/
A Dclk-mix.c37 if (mix->div_table) { in _get_maxdiv()
38 for (clkt = mix->div_table; clkt->div; clkt++) in _get_maxdiv()
54 if (mix->div_table) { in _get_div()
55 for (clkt = mix->div_table; clkt->div; clkt++) in _get_div()
91 if (mix->div_table) { in _get_div_val()
92 for (clkt = mix->div_table; clkt->div; clkt++) in _get_div_val()
A Dclk.h81 struct clk_div_table *div_table; member
91 struct clk_div_table *div_table; member
/linux/drivers/clk/
A Dclk-aspeed.c171 .div_table = ast2500_div_table,
178 .div_table = ast2400_div_table,
451 soc_data->div_table, in aspeed_clk_probe()
493 soc_data->div_table, in aspeed_clk_probe()
502 soc_data->div_table, in aspeed_clk_probe()
A Dclk-aspeed.h78 const struct clk_div_table *div_table; member
A Dclk-stm32f4.c537 const struct clk_div_table *div_table; member
574 const struct clk_div_table *div_table; member
841 div_data[i].div_table, in stm32f4_rcc_register_pll()
1776 post_div->div_table, in stm32f4_rcc_init()
/linux/drivers/clk/rockchip/
A Dclk.c44 struct clk_div_table *div_table, int gate_offset, in rockchip_clk_register_branch() argument
99 div->table = div_table; in rockchip_clk_register_branch()
458 if (list->div_table) in rockchip_clk_register_branches()
464 list->div_flags, list->div_table, in rockchip_clk_register_branches()
507 list->div_flags, list->div_table, in rockchip_clk_register_branches()
A Dclk.h455 struct clk_div_table *div_table; member
536 .div_table = dt, \
595 .div_table = dt, \
725 .div_table = dt, \
/linux/arch/m68k/atari/
A Ddebug.c214 static int div_table[9] = in atari_init_scc_port() local
229 div = div_table[baud]; in atari_init_scc_port()
/linux/drivers/clk/x86/
A Dclk-cgu.h193 const struct clk_div_table *div_table; member
241 .div_table = _dtable, \
/linux/drivers/gpu/drm/i915/display/
A Dintel_cdclk.c298 const u8 *div_table; in g33_get_cdclk() local
313 div_table = div_3200; in g33_get_cdclk()
316 div_table = div_4000; in g33_get_cdclk()
319 div_table = div_4800; in g33_get_cdclk()
322 div_table = div_5333; in g33_get_cdclk()
329 div_table[cdclk_sel]); in g33_get_cdclk()
380 const u8 *div_table; in i965gm_get_cdclk() local
395 div_table = div_3200; in i965gm_get_cdclk()
398 div_table = div_4000; in i965gm_get_cdclk()
401 div_table = div_5333; in i965gm_get_cdclk()
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/linux/drivers/net/ethernet/stmicro/stmmac/
A Ddwmac-meson8b.c151 static const struct clk_div_table div_table[] = { in meson8b_init_rgmii_tx_clk() local
181 clk_configs->m250_div.table = div_table; in meson8b_init_rgmii_tx_clk()
/linux/drivers/clk/qcom/
A Dgcc-ipq4019.c76 const struct clk_div_table *div_table; member
1394 for (clkt = pll->div_table; clkt->div; clkt++) { in clk_regmap_clk_div_recalc_rate()
1507 .div_table = fepllwcss_clk_div_table,
1525 .div_table = fepllwcss_clk_div_table,

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