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Searched refs:dmar_writeq (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/iommu/intel/
A Dsvm.c127 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); in intel_svm_enable_prq()
128 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); in intel_svm_enable_prq()
129 dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER); in intel_svm_enable_prq()
150 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); in intel_svm_finish_prq()
151 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); in intel_svm_finish_prq()
152 dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL); in intel_svm_finish_prq()
991 dmar_writeq(iommu->reg + DMAR_PQH_REG, tail); in prq_event_thread()
A Dpasid.c37 dmar_writeq(iommu->reg + DMAR_VCMD_REG, VCMD_CMD_ALLOC); in vcmd_alloc_pasid()
67 dmar_writeq(iommu->reg + DMAR_VCMD_REG, in vcmd_free_pasid()
A Diommu.c1449 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr); in iommu_set_root_entry()
1508 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); in __iommu_flush_context()
1556 dmar_writeq(iommu->reg + tlb_offset, val_iva); in __iommu_flush_iotlb()
1557 dmar_writeq(iommu->reg + tlb_offset + 8, val); in __iommu_flush_iotlb()
A Dirq_remapping.c483 dmar_writeq(iommu->reg + DMAR_IRTA_REG, in iommu_set_irq_remapping()
A Ddmar.c1691 dmar_writeq(iommu->reg + DMAR_IQA_REG, val); in __dmar_enable_qi()
/linux/include/linux/
A Dintel-iommu.h138 #define dmar_writeq(a,v) writeq(v,a) macro

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