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Searched refs:gpu_read (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/gpu/drm/panfrost/
A Dpanfrost_gpu.c25 u32 state = gpu_read(pfdev, GPU_INT_STAT); in panfrost_gpu_irq_handler()
26 u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS); in panfrost_gpu_irq_handler()
32 u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32; in panfrost_gpu_irq_handler()
33 address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO); in panfrost_gpu_irq_handler()
118 quirks = gpu_read(pfdev, GPU_TILER_CONFIG); in panfrost_gpu_init_quirks()
127 quirks = gpu_read(pfdev, GPU_L2_MMU_CONFIG); in panfrost_gpu_init_quirks()
221 pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES); in panfrost_gpu_init_features()
235 pfdev->features.as_present = gpu_read(pfdev, GPU_AS_PRESENT); in panfrost_gpu_init_features()
237 pfdev->features.js_present = gpu_read(pfdev, GPU_JS_PRESENT); in panfrost_gpu_init_features()
257 gpu_id = gpu_read(pfdev, GPU_ID); in panfrost_gpu_init_features()
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A Dpanfrost_regs.h322 #define gpu_read(dev, reg) readl(dev->iomem + reg) macro
/linux/drivers/gpu/drm/etnaviv/
A Detnaviv_gpu.c189 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs()
531 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset()
558 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset()
586 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); in etnaviv_gpu_enable_mlcg()
899 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); in etnaviv_gpu_debugfs()
900 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); in etnaviv_gpu_debugfs()
901 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); in etnaviv_gpu_debugfs()
902 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_gpu_debugfs()
1302 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in sync_point_perfmon_sample_pre()
1437 status = gpu_read(gpu, status_reg); in dump_mmu_fault()
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A Detnaviv_perfmon.c46 return gpu_read(gpu, domain->profile_read); in perf_reg_read()
61 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_perf_reg_read()
80 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_reg_read()
86 value += gpu_read(gpu, signal->data); in pipe_reg_read()
106 return gpu_read(gpu, reg); in hi_total_cycle_read()
120 return gpu_read(gpu, reg); in hi_total_idle_cycle_read()
A Detnaviv_iommu_v2.c172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
196 if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE) in etnaviv_iommuv2_restore_sec()
A Detnaviv_gpu.h156 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() function
A Detnaviv_sched.c108 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in etnaviv_sched_timedout_job()
A Detnaviv_dump.c89 reg->value = cpu_to_le32(gpu_read(gpu, etnaviv_dump_registers[i])); in etnaviv_core_dump_registers()
/linux/drivers/gpu/drm/msm/adreno/
A Da5xx_gpu.c1019 gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); in a5xx_recover()
1087 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_idle()
1089 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_idle()
1090 gpu_read(gpu, REG_A5XX_CP_RB_WPTR)); in a5xx_idle()
1133 gpu_read(gpu, REG_A5XX_CP_HW_FAULT)); in a5xx_cp_err_irq()
1233 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_fault_detect_irq()
1234 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_fault_detect_irq()
1235 gpu_read(gpu, REG_A5XX_CP_RB_WPTR), in a5xx_fault_detect_irq()
1237 gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ), in a5xx_fault_detect_irq()
1239 gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ)); in a5xx_fault_detect_irq()
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A Da2xx_gpu.c256 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a2xx_recover()
264 gpu_read(gpu, REG_A2XX_RBBM_SOFT_RESET); in a2xx_recover()
288 if (spin_until(!(gpu_read(gpu, REG_A2XX_RBBM_STATUS) & in a2xx_idle()
303 mstatus = gpu_read(gpu, REG_A2XX_MASTER_INT_SIGNAL); in a2xx_irq()
306 status = gpu_read(gpu, REG_A2XX_MH_INTERRUPT_STATUS); in a2xx_irq()
310 gpu_read(gpu, REG_A2XX_MH_MMU_PAGE_FAULT)); in a2xx_irq()
316 status = gpu_read(gpu, REG_AXXX_CP_INT_STATUS); in a2xx_irq()
326 status = gpu_read(gpu, REG_A2XX_RBBM_INT_STATUS); in a2xx_irq()
433 gpu_read(gpu, REG_A2XX_RBBM_STATUS)); in a2xx_dump()
446 state->rbbm_status = gpu_read(gpu, REG_A2XX_RBBM_STATUS); in a2xx_gpu_state_get()
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A Da6xx_gpu.c28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
45 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
46 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle()
47 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_idle()
48 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); in a6xx_idle()
1154 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); in a6xx_dump()
1317 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); in a6xx_cp_hw_err_irq()
1363 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_fault_detect_irq()
1364 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_fault_detect_irq()
1365 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), in a6xx_fault_detect_irq()
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A Da4xx_gpu.c278 val = gpu_read(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ); in a4xx_hw_init()
359 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a4xx_recover()
367 gpu_read(gpu, REG_A4XX_RBBM_SW_RESET_CMD); in a4xx_recover()
393 if (spin_until(!(gpu_read(gpu, REG_A4XX_RBBM_STATUS) & in a4xx_idle()
407 status = gpu_read(gpu, REG_A4XX_RBBM_INT_0_STATUS); in a4xx_irq()
411 uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS); in a4xx_irq()
561 state->rbbm_status = gpu_read(gpu, REG_A4XX_RBBM_STATUS); in a4xx_gpu_state_get()
569 gpu_read(gpu, REG_A4XX_RBBM_STATUS)); in a4xx_dump()
587 reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS); in a4xx_pm_resume()
618 ring->memptrs->rptr = gpu_read(gpu, REG_A4XX_CP_RB_RPTR); in a4xx_get_rptr()
A Da5xx_debugfs.c23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print()
36 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print()
49 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print()
64 val[j] = gpu_read(gpu, REG_A5XX_CP_ROQ_DBG_DATA); in roq_print()
A Da3xx_gpu.c360 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a3xx_recover()
368 gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD); in a3xx_recover()
394 if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) & in a3xx_idle()
409 status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS); in a3xx_irq()
463 gpu_read(gpu, REG_A3XX_RBBM_STATUS)); in a3xx_dump()
476 state->rbbm_status = gpu_read(gpu, REG_A3XX_RBBM_STATUS); in a3xx_gpu_state_get()
483 ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); in a3xx_get_rptr()
A Da6xx_gpu_state.c170 data[0] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2); in debugbus_read()
171 data[1] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1); in debugbus_read()
213 data[i] = gpu_read(gpu, REG_A6XX_VBIF_TEST_BUS_OUT); in vbif_debugbus_read()
243 clk = gpu_read(gpu, REG_A6XX_VBIF_CLKON); in a6xx_get_vbif_debugbus_block()
730 obj->data[index++] = gpu_read(gpu, in a6xx_get_ahb_gpu_registers()
881 obj->data[i] = gpu_read(gpu, indexed->data); in a6xx_get_indexed_regs()
901 mempool_size = gpu_read(gpu, REG_A6XX_CP_MEM_POOL_SIZE); in a6xx_get_indexed_registers()
927 bool stalled = !!(gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & in a6xx_gpu_state_get()
A Da5xx_gpu.h143 if ((gpu_read(gpu, reg) & mask) == value) in spin_usecs()
A Da5xx_preempt.c177 status = gpu_read(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL); in a5xx_preempt_irq()
A Da5xx_power.c267 u32 val = gpu_read(gpu, REG_A5XX_GPMU_GENERAL_1); in a5xx_gpmu_init()
A Dadreno_gpu.c557 state->registers[pos++] = gpu_read(gpu, addr); in adreno_gpu_state_get()
790 uint32_t val = gpu_read(gpu, addr); in adreno_dump()
A Da6xx_gmu.c1022 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & in a6xx_bus_clear_pending_transactions()
1031 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & in a6xx_bus_clear_pending_transactions()
1036 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & in a6xx_bus_clear_pending_transactions()
/linux/drivers/gpu/drm/msm/
A Dmsm_gpu.h429 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) in gpu_read() function
A Dmsm_gpu.c546 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg); in update_hw_cntrs()

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