| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_atomfirmware.c | 645 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
663 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
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| A D | gfx_v6_0.c | 1336 adev->gfx.config.max_sh_per_se); in gfx_v6_0_get_rb_active_bitmap()
1470 adev->gfx.config.max_sh_per_se; in gfx_v6_0_setup_rb()
1475 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1479 ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v6_0_setup_rb()
1503 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1551 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_spi()
1589 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1606 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1623 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1640 adev->gfx.config.max_sh_per_se = 1; in gfx_v6_0_constants_init()
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| A D | gfx_v7_0.c | 1632 adev->gfx.config.max_sh_per_se); in gfx_v7_0_get_rb_active_bitmap()
1792 adev->gfx.config.max_sh_per_se; in gfx_v7_0_setup_rb()
1797 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1800 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v7_0_setup_rb()
1826 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
3372 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_wait_for_rlc_serdes()
4290 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4307 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4325 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4343 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
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| A D | amdgpu_gfx.h | 150 unsigned max_sh_per_se; member
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| A D | gfx_v8_0.c | 1706 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1723 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1770 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1786 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1803 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1821 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
3478 adev->gfx.config.max_sh_per_se); in gfx_v8_0_get_rb_active_bitmap()
3640 adev->gfx.config.max_sh_per_se; in gfx_v8_0_setup_rb()
3645 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3674 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
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| A D | amdgpu_debugfs.c | 127 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
252 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_regs2_op()
735 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
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| A D | gfx_v9_0.c | 1813 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_init_always_on_cu_mask()
2523 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_rb_active_bitmap()
2534 adev->gfx.config.max_sh_per_se; in gfx_v9_0_setup_rb()
2538 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_setup_rb()
2541 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v9_0_setup_rb()
2680 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_wait_for_rlc_serdes()
4605 adev->gfx.config.max_sh_per_se; in gfx_v9_0_do_edc_gpr_workarounds()
7187 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_0_get_cu_info()
7192 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_cu_info()
7196 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_get_cu_info()
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| A D | gfxhub_v2_1.c | 543 adev->gfx.config.max_sh_per_se * in gfxhub_v2_1_utcl2_harvest()
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| A D | amdgpu_discovery.c | 552 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
571 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); in amdgpu_discovery_get_gfx_info()
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| A D | amdgpu_amdkfd.c | 467 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in amdgpu_amdkfd_get_cu_info()
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| A D | amdgpu_amdkfd_gfx_v9.c | 836 sh_cnt = adev->gfx.config.max_sh_per_se; in kgd_gfx_v9_get_cu_occupancy()
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| A D | gfx_v10_0.c | 5031 adev->gfx.config.max_sh_per_se); in gfx_v10_0_get_rb_active_bitmap()
5043 adev->gfx.config.max_sh_per_se; in gfx_v10_0_setup_rb()
5047 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_setup_rb()
5048 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_setup_rb()
5055 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v10_0_setup_rb()
5187 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_tcp_harvest()
9559 adev->gfx.config.max_sh_per_se * in gfx_v10_0_set_gds_init()
9634 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_get_cu_info()
9635 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_get_cu_info()
9686 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v10_3_get_disabled_sa()
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| A D | amdgpu_atombios.c | 728 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; in amdgpu_atombios_get_gfx_info()
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| A D | gfx_v9_4_2.c | 1886 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; in gfx_v9_4_2_query_sq_timeout_status()
1919 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; in gfx_v9_4_2_reset_sq_timeout_status()
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| A D | amdgpu_kms.c | 815 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in amdgpu_info_ioctl()
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| A D | amdgpu_device.c | 2012 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); in amdgpu_device_parse_gpu_info_fw()
3680 adev->gfx.config.max_sh_per_se, in amdgpu_device_init()
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| /linux/drivers/gpu/drm/radeon/ |
| A D | radeon_kms.c | 465 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()
467 *value = rdev->config.si.max_sh_per_se; in radeon_info_ioctl()
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| A D | si.c | 3102 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3119 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3137 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3154 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3171 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3288 rdev->config.si.max_sh_per_se, in si_gpu_init()
3292 rdev->config.si.max_sh_per_se, in si_gpu_init()
3297 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_gpu_init()
5324 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_init_ao_cu_mask()
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| A D | cik.c | 3181 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3198 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3216 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3234 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3336 rdev->config.cik.max_sh_per_se, in cik_gpu_init()
3341 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_gpu_init()
5787 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_wait_for_rlc_serdes()
6554 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_init_ao_cu_mask()
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| A D | radeon.h | 2163 unsigned max_sh_per_se; member
2194 unsigned max_sh_per_se; member
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| /linux/drivers/gpu/drm/amd/include/ |
| A D | atomfirmware.h | 1562 uint8_t max_sh_per_se; member
1582 uint8_t max_sh_per_se; member
1607 uint8_t max_sh_per_se; member
1642 uint8_t max_sh_per_se; member
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| A D | atombios.h | 5655 UCHAR max_sh_per_se; member
5668 UCHAR max_sh_per_se; member
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| A D | vangogh_ppt.c | 2011 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; in vangogh_post_smu_init()
2037 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; in vangogh_post_smu_init()
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