| /linux/Documentation/x86/ |
| A D | microcode.rst | 17 Early load microcode
20 The kernel can update microcode very early during boot. Loading
31 The microcode files in cpio name space are:
34 kernel/x86/microcode/GenuineIntel.bin
36 kernel/x86/microcode/AuthenticAMD.bin
39 scans the microcode file in the initrd. If microcode matching the
62 DSTDIR=kernel/x86/microcode
96 /dev/cpu/microcode or through /sys/devices/system/cpu/microcode/reload file
105 # echo 1 > /sys/devices/system/cpu/microcode/reload
109 The loading mechanism looks for microcode blobs in
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| A D | mds.rst | 77 instruction in combination with a microcode update. The microcode clears
87 executed on a CPU without the microcode update there is no side effect
102 the microcode updated, but the hypervisor does not (yet) expose the
124 scenarios where the host has the updated microcode but the
191 functionality in microcode. Aside of that the IO-Port mechanism is a
193 not affected or do not receive microcode updates anymore.
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| A D | index.rst | 29 microcode
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| A D | tsx_async_abort.rst | 26 microcode update which can be used to disable TSX. In addition, it
48 scenarios where the host has the updated microcode but the
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| /linux/Documentation/powerpc/ |
| A D | qe_firmware.rst | 45 integers that compose the actual QE microcode.
50 1) describes the microcode's purpose
51 2) describes how and where to upload the microcode
62 disables the microcode) must be performed first.
76 in the microcode.
178 the microcode.
211 the microcode to the SOC itself. Normally, the microcode loader should
241 'microcode' (type: struct qe_microcode):
246 identifies this particular microcode.
257 microcode.
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| A D | imc.rst | 21 The Nest PMU counters are handled by a Nest IMC microcode which runs in the OCC
22 (On-Chip Controller) complex. The microcode collects the counter data and moves
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| /linux/arch/x86/kernel/cpu/microcode/ |
| A D | Makefile | 2 microcode-y := core.o
3 obj-$(CONFIG_MICROCODE) += microcode.o
4 microcode-$(CONFIG_MICROCODE_INTEL) += intel.o
5 microcode-$(CONFIG_MICROCODE_AMD) += amd.o
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| A D | intel.c | 742 csig->rev = c->microcode; in collect_cpu_info()
817 c->microcode = rev; in apply_microcode_intel()
821 boot_cpu_data.microcode = rev; in apply_microcode_intel()
924 c->microcode < 0x0b000021) { in is_blacklisted()
925 …rr_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode); in is_blacklisted()
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| A D | amd.c | 659 csig->rev = c->microcode; in collect_cpu_info_amd()
715 c->microcode = rev; in apply_microcode_amd()
719 boot_cpu_data.microcode = rev; in apply_microcode_amd()
861 if (boot_cpu_data.microcode >= p->patch_id) in load_microcode_amd()
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| /linux/Documentation/power/ |
| A D | suspend-and-cpuhotplug.rst | 176 There are some interesting situations involving CPU hotplug and microcode
179 [Please bear in mind that the kernel requests the microcode images from
187 to apply the same microcode revision to each of the CPUs.
190 and thereby in applying the correct microcode revision to it.
208 (which is sent by the CPU hotplug code), the microcode update driver's
210 microcode image for that CPU.
213 doesn't have the microcode image, it does the CPU type/model discovery
221 have a valid microcode image. This ensures that the CPU type/model
226 d. Handling microcode update during suspend/hibernate:
246 the existing copy of microcode image in the kernel is not freed up.
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| /linux/Documentation/admin-guide/hw-vuln/ |
| A D | tsx_async_abort.rst | 100 * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
114 If the processor is vulnerable, but the availability of the microcode-based
120 microcode update applied, but the hypervisor is not yet updated to expose the
121 CPUID to the guest. If the host has updated microcode the protection takes
132 required. If a CPU is affected and the microcode is available, then the kernel
142 Affected systems where the host has TAA microcode and TAA is mitigated by
146 In all other cases, if the host either does not have the TAA microcode or
192 and which get the new IA32_TSX_CTRL MSR through a microcode
219 tsx=off tsx_async_abort=full TSX might be disabled if microcode
238 0 0 0 Vulnerable (needs microcode)
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| A D | special-register-buffer-data-sampling.rst | 64 Intel will release microcode updates that modify the RDRAND, RDSEED, and
86 The microcode updates provide an opt-out mechanism (RNGDS_MITG_DIS) to disable
100 9]==1. This MSR is introduced through the microcode update.
132 Vulnerable: No microcode Processor vulnerable and microcode is missing
147 This new microcode serializes processor access during execution of RDRAND,
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| A D | mds.rst | 104 * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
105 - The processor is vulnerable but microcode is not updated.
127 If the processor is vulnerable, but the availability of the microcode based
133 microcode update applied, but the hypervisor is not yet updated to expose
134 the CPUID to the guest. If the host has updated microcode the protection
143 The kernel detects the affected CPUs and the presence of the microcode
146 If a CPU is affected and the microcode is available, then the kernel
176 If the L1D flush mitigation is enabled and up to date microcode is
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| /linux/drivers/net/wireless/intel/iwlegacy/ |
| A D | Kconfig | 22 In order to use this driver, you will need a microcode (uCode)
23 image for it. You can obtain the microcode from:
27 The microcode is typically installed in /lib/firmware. You can
49 In order to use this driver, you will need a microcode (uCode)
50 image for it. You can obtain the microcode from:
54 The microcode is typically installed in /lib/firmware. You can
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| /linux/drivers/crypto/cavium/cpt/ |
| A D | cptpf.h | 22 struct microcode { struct
53 struct microcode mcode[CPT_MAX_CORE_GROUPS]; argument
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| A D | cptpf_main.c | 122 static int cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode) in cpt_load_microcode()
160 static int do_cpt_init(struct cpt_device *cpt, struct microcode *mcode) in do_cpt_init()
256 struct microcode *mcode; in cpt_ucode_load_fw()
415 struct microcode *mcode = &cpt->mcode[grp]; in cpt_unload_microcode()
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| /linux/arch/x86/kernel/cpu/ |
| A D | proc.c | 83 if (c->microcode) in show_cpuinfo()
84 seq_printf(m, "microcode\t: 0x%x\n", c->microcode); in show_cpuinfo()
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| A D | intel.c | 136 u32 microcode; member
179 return (c->microcode <= spectre_bad_microcodes[i].microcode); in bad_spectre_microcode()
202 c->microcode = intel_get_microcode_revision(); in early_init_intel()
229 c->microcode < 0x20e) { in early_init_intel()
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| A D | match.c | 86 if (!res || res->x86_microcode_rev > boot_cpu_data.microcode) in x86_cpu_has_min_microcode_rev()
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| A D | Makefile | 50 obj-$(CONFIG_MICROCODE) += microcode/
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| /linux/drivers/soc/fsl/qe/ |
| A D | qe.c | 483 calc_size = struct_size(firmware, microcode, firmware->count); in qe_upload_firmware()
492 be32_to_cpu(firmware->microcode[i].count); in qe_upload_firmware()
534 const struct qe_microcode *ucode = &firmware->microcode[i]; in qe_upload_firmware()
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| /linux/arch/x86/include/uapi/asm/ |
| A D | mce.h | 37 __u32 microcode; /* Microcode revision */ member
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| /linux/Documentation/process/ |
| A D | changes.rst | 242 Intel IA32 microcode
245 A driver has been added to allow updating of Intel IA32 microcode,
250 mknod /dev/cpu/microcode c 10 184
251 chmod 0644 /dev/cpu/microcode
441 Intel P6 microcode
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| /linux/Documentation/ |
| A D | Changes | 242 Intel IA32 microcode
245 A driver has been added to allow updating of Intel IA32 microcode,
250 mknod /dev/cpu/microcode c 10 184
251 chmod 0644 /dev/cpu/microcode
441 Intel P6 microcode
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| /linux/drivers/net/wan/ |
| A D | cosa.c | 1365 static int download(struct cosa_data *cosa, const char __user *microcode, int length, int address) in download() argument
1394 if (get_user(c, microcode)) in download()
1397 c = *microcode; in download()
1401 microcode++; in download()
1458 static int readmem(struct cosa_data *cosa, char __user *microcode, int length, int address) in readmem() argument
1494 if (put_user(c, microcode)) in readmem()
1497 *microcode = c; in readmem()
1499 microcode++; in readmem()
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