Searched refs:mmMMSCH_VF_MAILBOX_RESP (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | mmsch_v2_0.h | 67 #define mmMMSCH_VF_MAILBOX_RESP … macro
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| A D | vcn_v2_0.c | 1807 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v2_0_start_mmsch()
1824 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_0_start_mmsch()
1828 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_0_start_mmsch()
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| A D | vcn_v2_5.c | 1123 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v2_5_mmsch_start()
1131 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_5_mmsch_start()
1135 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_5_mmsch_start()
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| A D | vcn_v3_0.c | 1445 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v3_0_start_sriov()
1457 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v3_0_start_sriov()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| A D | vcn_2_5_offset.h | 37 #define mmMMSCH_VF_MAILBOX_RESP … macro
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| A D | vcn_3_0_0_offset.h | 65 #define mmMMSCH_VF_MAILBOX_RESP … macro
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