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Searched refs:mmMP0_SMN_C2PMSG_101 (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dpsp_v11_0_8.c65 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_8_ring_stop()
70 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v11_0_8_ring_stop()
109 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_8_ring_create()
116 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v11_0_8_ring_create()
190 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_8_ring_set_wptr()
A Dpsp_v3_1.c247 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg); in psp_v3_1_ring_create()
254 mmMP0_SMN_C2PMSG_101), 0x80000000, in psp_v3_1_ring_create()
292 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v3_1_ring_stop()
303 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v3_1_ring_stop()
392 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v3_1_ring_set_wptr()
A Dpsp_v12_0.c274 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v12_0_ring_create()
281 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v12_0_ring_create()
318 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v12_0_ring_stop()
329 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v12_0_ring_stop()
409 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); in psp_v12_0_ring_set_wptr()
A Dpsp_v11_0.c445 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_ring_stop()
456 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v11_0_ring_stop()
489 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_ring_create()
496 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v11_0_ring_create()
760 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); in psp_v11_0_ring_set_wptr()
/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
A Dmp_10_0_offset.h166 #define mmMP0_SMN_C2PMSG_101 macro
A Dmp_12_0_0_offset.h166 #define mmMP0_SMN_C2PMSG_101 macro
A Dmp_11_0_offset.h166 #define mmMP0_SMN_C2PMSG_101 macro
A Dmp_11_0_8_offset.h166 #define mmMP0_SMN_C2PMSG_101 macro
A Dmp_9_0_offset.h166 #define mmMP0_SMN_C2PMSG_101 0x00a5 macro
A Dmp_11_5_0_offset.h166 #define mmMP0_SMN_C2PMSG_101 macro

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