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Searched refs:mmMP0_SMN_C2PMSG_102 (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dpsp_v11_0_8.c103 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); in psp_v11_0_8_ring_create()
177 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); in psp_v11_0_8_ring_get_wptr()
189 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); in psp_v11_0_8_ring_set_wptr()
A Dpsp_v12_0.c268 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); in psp_v12_0_ring_create()
396 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); in psp_v12_0_ring_get_wptr()
408 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); in psp_v12_0_ring_set_wptr()
A Dpsp_v3_1.c239 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); in psp_v3_1_ring_create()
390 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); in psp_v3_1_ring_set_wptr()
A Dpsp_v11_0.c483 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); in psp_v11_0_ring_create()
759 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); in psp_v11_0_ring_set_wptr()
/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
A Dmp_10_0_offset.h168 #define mmMP0_SMN_C2PMSG_102 macro
A Dmp_12_0_0_offset.h168 #define mmMP0_SMN_C2PMSG_102 macro
A Dmp_11_0_offset.h168 #define mmMP0_SMN_C2PMSG_102 macro
A Dmp_11_0_8_offset.h168 #define mmMP0_SMN_C2PMSG_102 macro
A Dmp_9_0_offset.h168 #define mmMP0_SMN_C2PMSG_102 0x00a6 macro
A Dmp_11_5_0_offset.h168 #define mmMP0_SMN_C2PMSG_102 macro

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