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Searched refs:mmSCRATCH_REG0_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
A Dgc_9_4_1_offset.h214 #define mmSCRATCH_REG0_BASE_IDX macro
A Dgc_9_0_offset.h4642 #define mmSCRATCH_REG0_BASE_IDX macro
A Dgc_9_1_offset.h4872 #define mmSCRATCH_REG0_BASE_IDX macro
A Dgc_9_2_1_offset.h4828 #define mmSCRATCH_REG0_BASE_IDX macro
A Dgc_10_1_0_offset.h7106 #define mmSCRATCH_REG0_BASE_IDX macro
A Dgc_10_3_0_offset.h6731 #define mmSCRATCH_REG0_BASE_IDX macro
/linux/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v10_0.c1513 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4; in gfx_v10_rlcg_rw()
1517 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4; in gfx_v10_rlcg_rw()
A Dgfx_v9_0.c752 …scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_w()

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