| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_mpc.c | 44 mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name
165 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_output_csc()
167 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_output_csc()
223 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_ocsc_default()
225 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_ocsc_default()
251 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field()
259 reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field()
263 reg->masks.field_region_end_base = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; in mpc2_ogam_get_reg_field()
267 reg->masks.exp_region_start = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_B; in mpc2_ogam_get_reg_field()
566 const struct dcn20_mpc_mask *mpc_mask, in dcn20_mpc_construct() argument
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| A D | dcn20_mpc.h | 267 const struct dcn20_mpc_mask *mpc_mask; member
274 const struct dcn20_mpc_mask *mpc_mask,
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| A D | dcn20_resource.c | 851 static const struct dcn20_mpc_mask mpc_mask = { variable
1222 &mpc_mask, in dcn20_mpc_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_mpc.c | 41 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
182 reg->masks.field_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_OFFSET_B; in mpc3_ogam_get_reg_field()
1086 gam_regs.masks.csc_c12 = mpc30->mpc_mask->MPCC_GAMUT_REMAP_C12_A; in program_gamut_remap()
1256 ocsc_regs.masks.csc_c11 = mpc30->mpc_mask->MPC_OCSC_C11_A; in mpc3_set_output_csc()
1258 ocsc_regs.masks.csc_c12 = mpc30->mpc_mask->MPC_OCSC_C12_A; in mpc3_set_output_csc()
1298 ocsc_regs.masks.csc_c11 = mpc30->mpc_mask->MPC_OCSC_C11_A; in mpc3_set_ocsc_default()
1300 ocsc_regs.masks.csc_c12 = mpc30->mpc_mask->MPC_OCSC_C12_A; in mpc3_set_ocsc_default()
1390 if (mpc30->mpc_mask->MPC_RMU0_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPC_RMU1_MEM_LOW_PWR_MODE) { in mpc3_set_mpc_mem_lp_mode()
1395 if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) { in mpc3_set_mpc_mem_lp_mode()
1440 const struct dcn30_mpc_mask *mpc_mask, in dcn30_mpc_construct() argument
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| A D | dcn30_mpc.h | 783 const struct dcn30_mpc_mask *mpc_mask; member
791 const struct dcn30_mpc_mask *mpc_mask,
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| A D | dcn30_resource.c | 681 static const struct dcn30_mpc_mask mpc_mask = { variable
988 &mpc_mask, in dcn30_mpc_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_mpc.c | 40 mpc201->mpc_shift->field_name, mpc201->mpc_mask->field_name
107 const struct dcn201_mpc_mask *mpc_mask, in dcn201_mpc_construct() argument
118 mpc201->mpc_mask = mpc_mask; in dcn201_mpc_construct()
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| A D | dcn201_mpc.h | 76 const struct dcn201_mpc_mask *mpc_mask; member
83 const struct dcn201_mpc_mask *mpc_mask,
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| A D | dcn201_resource.c | 497 static const struct dcn201_mpc_mask mpc_mask = { variable
736 &mpc_mask, in dcn201_mpc_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_mpc.c | 37 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
506 const struct dcn_mpc_mask *mpc_mask, in dcn10_mpc_construct() argument
517 mpc10->mpc_mask = mpc_mask; in dcn10_mpc_construct()
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| A D | dcn10_mpc.h | 131 const struct dcn_mpc_mask *mpc_mask; member
138 const struct dcn_mpc_mask *mpc_mask,
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| A D | dcn10_resource.c | 447 static const struct dcn_mpc_mask mpc_mask = { variable
753 &mpc_mask, in dcn10_mpc_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| A D | dcn301_resource.c | 525 static const struct dcn30_mpc_mask mpc_mask = { variable
825 &mpc_mask, in dcn301_mpc_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn302/ |
| A D | dcn302_resource.c | 779 static const struct dcn30_mpc_mask mpc_mask = { variable
790 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); in dcn302_mpc_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn303/ |
| A D | dcn303_resource.c | 724 static const struct dcn30_mpc_mask mpc_mask = { variable
735 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); in dcn303_mpc_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_resource.c | 520 static const struct dcn20_mpc_mask mpc_mask = { variable
1532 &mpc_mask, in dcn21_mpc_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_resource.c | 744 static const struct dcn30_mpc_mask mpc_mask = { variable
1161 &mpc_mask, in dcn31_mpc_create()
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