Searched refs:num_clk (Results 1 – 8 of 8) sorted by relevance
| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| A D | dpu_io_util.c | 20 for (i = num_clk - 1; i >= 0; i--) { in msm_dss_put_clk()
31 for (i = 0; i < num_clk; i++) { in msm_dss_get_clk()
58 for (i = 0; i < num_clk; i++) { in msm_dss_clk_set_rate()
92 for (i = 0; i < num_clk; i++) { in msm_dss_enable_clk()
110 for (i = num_clk - 1; i >= 0; i--) { in msm_dss_enable_clk()
127 int num_clk = 0; in msm_dss_parse_clock() local
132 mp->num_clk = 0; in msm_dss_parse_clock()
134 if (num_clk <= 0) { in msm_dss_parse_clock()
145 for (i = 0; i < num_clk; i++) { in msm_dss_parse_clock()
172 for (i = 0; i < num_clk; i++) { in msm_dss_parse_clock()
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| A D | dpu_io_util.h | 30 unsigned int num_clk; member
34 int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk);
35 void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk);
36 int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk);
37 int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable);
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| A D | dpu_mdss.c | 142 ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); in dpu_mdss_enable()
180 ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false); in dpu_mdss_disable()
200 msm_dss_put_clk(mp->clk_config, mp->num_clk); in dpu_mdss_destroy()
266 msm_dss_put_clk(mp->clk_config, mp->num_clk); in dpu_mdss_init()
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| A D | dpu_kms.c | 945 for (i = 0; i < mp->num_clk; i++) { in _dpu_kms_get_clk()
1208 msm_dss_put_clk(mp->clk_config, mp->num_clk); in dpu_unbind()
1210 mp->num_clk = 0; in dpu_unbind()
1241 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false); in dpu_runtime_suspend()
1268 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); in dpu_runtime_resume()
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| /linux/drivers/gpu/drm/msm/dp/ |
| A D | dp_parser.c | 128 int num_clk, i, rc; in dp_parser_init_clk_data() local
137 if (num_clk <= 0) { in dp_parser_init_clk_data()
142 for (i = 0; i < num_clk; i++) { in dp_parser_init_clk_data()
164 core_power->num_clk = core_clk_count; in dp_parser_init_clk_data()
177 ctrl_power->num_clk = ctrl_clk_count; in dp_parser_init_clk_data()
182 ctrl_power->num_clk = 0; in dp_parser_init_clk_data()
197 stream_power->num_clk = 0; in dp_parser_init_clk_data()
207 int num_clk = 0; in dp_parser_clock() local
222 core_clk_count = core_power->num_clk; in dp_parser_clock()
223 ctrl_clk_count = ctrl_power->num_clk; in dp_parser_clock()
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| A D | dp_power.c | 108 rc = msm_dss_get_clk(dev, core->clk_config, core->num_clk); in dp_power_clk_init()
115 rc = msm_dss_get_clk(dev, ctrl->clk_config, ctrl->num_clk); in dp_power_clk_init()
119 msm_dss_put_clk(core->clk_config, core->num_clk); in dp_power_clk_init()
127 msm_dss_put_clk(core->clk_config, core->num_clk); in dp_power_clk_init()
147 msm_dss_put_clk(ctrl->clk_config, ctrl->num_clk); in dp_power_clk_deinit()
148 msm_dss_put_clk(core->clk_config, core->num_clk); in dp_power_clk_deinit()
149 msm_dss_put_clk(stream->clk_config, stream->num_clk); in dp_power_clk_deinit()
154 struct dss_clk *clk_arry, int num_clk, int enable) in dp_power_clk_set_link_rate() argument
159 for (i = 0; i < num_clk; i++) { in dp_power_clk_set_link_rate()
192 rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk); in dp_power_clk_set_rate()
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| A D | dp_ctrl.c | 1292 u32 num = ctrl->parser->mp[module].num_clk; in dp_ctrl_set_clock_rate()
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| /linux/drivers/gpu/drm/exynos/ |
| A D | exynos_drm_scaler.c | 34 unsigned int num_clk; member
515 for (i = 0; i < scaler->scaler_data->num_clk; ++i) { in scaler_probe()
567 for (i = 0; i < scaler->scaler_data->num_clk; ++i) in scaler_clk_ctrl()
703 .num_clk = 1,
710 .num_clk = 3,
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