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Searched refs:phy_write (Results 1 – 25 of 89) sorted by relevance

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/linux/drivers/net/phy/
A Dvitesse.c134 phy_write(phydev, 0x1f, 0x2a30); in vsc73xx_config_init()
136 phy_write(phydev, 0x1f, 0x0000); in vsc73xx_config_init()
150 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
152 phy_write(phydev, 0x1f, 0x52b5); in vsc738x_config_init()
153 phy_write(phydev, 0x10, 0xb68a); in vsc738x_config_init()
156 phy_write(phydev, 0x10, 0x968a); in vsc738x_config_init()
157 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
159 phy_write(phydev, 0x1f, 0x0000); in vsc738x_config_init()
183 phy_write(phydev, 0x1f, 0x0000); in vsc738x_config_init()
184 phy_write(phydev, 0x12, 0x0048); in vsc738x_config_init()
[all …]
A Dnational.c54 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_read()
60 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_write()
61 phy_write(phydev, NS_EXP_MEM_DATA, data); in ns_exp_write()
108 err = phy_write(phydev, DP83865_INT_MASK, in ns_config_intr()
111 err = phy_write(phydev, DP83865_INT_MASK, 0); in ns_config_intr()
125 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN)); in ns_giga_speed_fallback()
128 phy_write(phydev, NS_EXP_MEM_CTL, 0); in ns_giga_speed_fallback()
129 phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0); in ns_giga_speed_fallback()
130 phy_write(phydev, NS_EXP_MEM_DATA, 0x0008); in ns_giga_speed_fallback()
131 phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN)); in ns_giga_speed_fallback()
[all …]
A Dmeson-gxl.c55 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
58 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
61 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
64 return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
69 phy_write(phydev, TSTCNTL, 0); in meson_gxl_close_banks()
81 ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ | in meson_gxl_read_reg()
105 ret = phy_write(phydev, TSTWRITE, value); in meson_gxl_write_reg()
109 ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE | in meson_gxl_write_reg()
218 ret = phy_write(phydev, INTSRC_MASK, val); in meson_gxl_config_intr()
221 ret = phy_write(phydev, INTSRC_MASK, val); in meson_gxl_config_intr()
A Drockchip.c47 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
51 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_init_tstmode()
55 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
61 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_close_tstmode()
76 ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB); in rockchip_integrated_phy_analog_init()
79 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG); in rockchip_integrated_phy_analog_init()
98 ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_integrated_phy_config_init()
147 err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_set_polarity()
A Ddavicom.c87 err = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
90 err = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
123 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_aneg()
142 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_init()
159 err = phy_write(phydev, MII_DM9161_SCR, temp); in dm9161_config_init()
164 err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT); in dm9161_config_init()
170 return phy_write(phydev, MII_BMCR, BMCR_ANENABLE); in dm9161_config_init()
A Dbcm7xxx.c80 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
108 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
271 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
281 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
337 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
341 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
347 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
383 phy_write(phydev, MII_BMCR, in bcm7xxx_28nm_ephy_eee_enable()
716 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00); in bcm7xxx_config_init()
720 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00); in bcm7xxx_config_init()
[all …]
A Ddp83tc811.c217 err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status); in dp83811_config_intr()
232 err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status); in dp83811_config_intr()
244 err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status); in dp83811_config_intr()
247 err = phy_write(phydev, MII_DP83811_INT_STAT1, 0); in dp83811_config_intr()
251 err = phy_write(phydev, MII_DP83811_INT_STAT2, 0); in dp83811_config_intr()
255 err = phy_write(phydev, MII_DP83811_INT_STAT3, 0); in dp83811_config_intr()
316 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
321 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
337 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
340 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
[all …]
A Dbcm-phy-lib.c127 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_write_misc()
134 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_write_misc()
151 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_read_misc()
158 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_read_misc()
196 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_phy_config_intr()
199 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_phy_config_intr()
250 return phy_write(phydev, MII_BCM54XX_SHD, in bcm_phy_write_shadow()
589 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd); in bcm_phy_28nm_a0b0_afe_config_init()
653 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); in _bcm_phy_cable_test_start()
654 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); in _bcm_phy_cable_test_start()
[all …]
A Dmicrochip.c40 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF); in lan88xx_phy_config_intr()
42 rc = phy_write(phydev, LAN88XX_INT_MASK, in lan88xx_phy_config_intr()
46 rc = phy_write(phydev, LAN88XX_INT_MASK, 0); in lan88xx_phy_config_intr()
260 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg); in lan88xx_probe()
312 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1); in lan88xx_set_mdix()
316 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf); in lan88xx_set_mdix()
317 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0); in lan88xx_set_mdix()
A Dbcm63xx.c34 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_intr()
37 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_intr()
60 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_init()
69 return phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_init()
A Dcicada.c67 err = phy_write(phydev, MII_CIS8201_AUX_CONSTAT, in cis820x_config_init()
73 err = phy_write(phydev, MII_CIS8201_EXT_CON1, in cis820x_config_init()
95 err = phy_write(phydev, MII_CIS8201_IMASK, in cis820x_config_intr()
98 err = phy_write(phydev, MII_CIS8201_IMASK, 0); in cis820x_config_intr()
A Dsmsc.c72 rc = phy_write(phydev, MII_LAN83C185_IM, intmask); in smsc_phy_config_intr()
74 rc = phy_write(phydev, MII_LAN83C185_IM, intmask); in smsc_phy_config_intr()
122 rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS, in smsc_phy_config_init()
142 phy_write(phydev, MII_LAN83C185_SPECIAL_MODES, rc); in smsc_phy_reset()
182 phy_write(phydev, SPECIAL_CTRL_STS, rc); in lan87xx_config_aneg()
201 phy_write(phydev, PHY_EDPD_CONFIG, rc); in lan95xx_config_aneg_ext()
226 rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS, in lan87xx_read_status()
246 rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS, in lan87xx_read_status()
A Dlxt.c88 err = phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN); in lxt970_config_intr()
90 err = phy_write(phydev, MII_LXT970_IER, 0); in lxt970_config_intr()
129 return phy_write(phydev, MII_LXT970_CONFIG, 0); in lxt970_config_init()
152 err = phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN); in lxt971_config_intr()
154 err = phy_write(phydev, MII_LXT971_IER, 0); in lxt971_config_intr()
292 phy_write(phydev, MII_BMCR, val); in lxt973_probe()
A Ddp83869.c208 err = phy_write(phydev, MII_DP83869_MICR, micr_status); in dp83869_config_intr()
210 err = phy_write(phydev, MII_DP83869_MICR, micr_status); in dp83869_config_intr()
336 return phy_write(phydev, MII_DP83869_MICR, val_micr); in dp83869_set_wol()
623 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val); in dp83869_configure_rgmii()
701 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT); in dp83869_configure_mode()
711 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
738 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
749 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
755 ret = phy_write(phydev, MII_DP83869_PHYCTRL, in dp83869_configure_mode()
800 phy_write(phydev, DP83869_CFG4, val); in dp83869_config_init()
[all …]
A Dbroadcom.c79 phy_write(phydev, MII_CTRL1000, val); in bcm54210e_config_init()
325 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm54xx_config_init()
333 err = phy_write(phydev, MII_BCM54XX_IMR, reg); in bcm54xx_config_init()
424 ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN); in bcm54xx_suspend()
593 return phy_write(phydev, reg, val | set); in brcm_phy_setbits()
601 err = phy_write(phydev, MII_BMCR, BMCR_RESET); in brcm_fet_config_init()
616 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_init()
627 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); in brcm_fet_config_init()
641 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); in brcm_fet_config_init()
692 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_intr()
[all …]
A Drealtek.c184 err = phy_write(phydev, RTL821x_INER, in rtl8211b_config_intr()
187 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211b_config_intr()
206 err = phy_write(phydev, RTL821x_INER, in rtl8211e_config_intr()
209 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211e_config_intr()
315 phy_write(phydev, 0x17, 0x2138); in rtl8211_config_aneg()
316 phy_write(phydev, 0x0e, 0x0260); in rtl8211_config_aneg()
318 phy_write(phydev, 0x17, 0x2108); in rtl8211_config_aneg()
319 phy_write(phydev, 0x0e, 0x0000); in rtl8211_config_aneg()
477 phy_write(phydev, MII_MMD_DATA, BIT(9)); in rtl8211b_suspend()
484 phy_write(phydev, MII_MMD_DATA, 0); in rtl8211b_resume()
[all …]
A Dqsemi.c71 return phy_write(phydev, MII_QS6612_PCR, 0x0dc0); in qs6612_config_init()
110 err = phy_write(phydev, MII_QS6612_IMR, in qs6612_config_intr()
113 err = phy_write(phydev, MII_QS6612_IMR, 0); in qs6612_config_intr()
A Dmicrel.c161 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); in kszphy_extended_write()
167 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); in kszphy_extended_read()
197 phy_write(phydev, MII_KSZPHY_CTRL, temp); in kszphy_config_intr()
206 err = phy_write(phydev, MII_KSZPHY_INTCS, temp); in kszphy_config_intr()
209 err = phy_write(phydev, MII_KSZPHY_INTCS, temp); in kszphy_config_intr()
250 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); in kszphy_rmii_clk_sel()
276 rc = phy_write(phydev, reg, temp); in kszphy_setup_led()
314 ret = phy_write(phydev, MII_KSZPHY_OMSO, in kszphy_nand_tree_disable()
892 result = phy_write(phydev, MII_CTRL1000, result); in ksz9031_config_init()
1580 phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, in lanphy_read_page_reg()
[all …]
A Dste10Xp.c40 err = phy_write(phydev, MII_BMCR, value); in ste10Xp_config_init()
72 err = phy_write(phydev, MII_XIE, MII_XIE_DEFAULT_MASK); in ste10Xp_config_intr()
74 err = phy_write(phydev, MII_XIE, 0); in ste10Xp_config_intr()
/linux/drivers/net/ethernet/realtek/
A Dr8169_phy_config.c285 phy_write(phydev, 0x1f, 0x0001); in rtl8168bb_hw_phy_config()
287 phy_write(phydev, 0x10, 0xf41b); in rtl8168bb_hw_phy_config()
288 phy_write(phydev, 0x1f, 0x0000); in rtl8168bb_hw_phy_config()
300 phy_write(phydev, 0x1d, 0x0f00); in rtl8168cp_1_hw_phy_config()
447 phy_write(phydev, 0x1f, 0x0005); in rtl8168d_apply_firmware_cond()
448 phy_write(phydev, 0x05, 0x001b); in rtl8168d_apply_firmware_cond()
450 phy_write(phydev, 0x1f, 0x0000); in rtl8168d_apply_firmware_cond()
467 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
497 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
502 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
[all …]
/linux/drivers/net/ethernet/ibm/emac/
A Dphy.c33 #define phy_write _phy_write macro
63 phy_write(phy, MII_BMCR, val); in emac_mii_reset_phy()
126 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
164 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
201 phy_write(phy, MII_BMCR, ctl); in genmii_setup_forced()
370 phy_write(phy, 0x14, 0x0ce3); in m88e1111_init()
371 phy_write(phy, 0x18, 0x4101); in m88e1111_init()
372 phy_write(phy, 0x09, 0x0e00); in m88e1111_init()
373 phy_write(phy, 0x04, 0x01e1); in m88e1111_init()
374 phy_write(phy, 0x00, 0x9140); in m88e1111_init()
[all …]
/linux/drivers/phy/freescale/
A Dphy-fsl-imx8-mipi-dphy.c333 phy_write(phy, 0x00, DPHY_LOCK_BYP); in mixel_dphy_configure()
338 phy_write(phy, 0x25, DPHY_TST); in mixel_dphy_configure()
361 phy_write(phy, PWR_OFF, DPHY_PD_PLL); in mixel_dphy_init()
362 phy_write(phy, PWR_OFF, DPHY_PD_DPHY); in mixel_dphy_init()
369 phy_write(phy, 0, DPHY_CM); in mixel_dphy_exit()
370 phy_write(phy, 0, DPHY_CN); in mixel_dphy_exit()
371 phy_write(phy, 0, DPHY_CO); in mixel_dphy_exit()
386 phy_write(phy, PWR_ON, DPHY_PD_PLL); in mixel_dphy_power_on()
394 phy_write(phy, PWR_ON, DPHY_PD_DPHY); in mixel_dphy_power_on()
406 phy_write(phy, PWR_OFF, DPHY_PD_PLL); in mixel_dphy_power_off()
[all …]
/linux/arch/powerpc/platforms/85xx/
A Dmpc85xx_mds.c75 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK)); in mpc8568_fixup_125_clock()
80 err = phy_write(phydev, MII_BMCR, BMCR_RESET); in mpc8568_fixup_125_clock()
90 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008); in mpc8568_fixup_125_clock()
101 err = phy_write(phydev,29, 0x0006); in mpc8568_mds_phy_fixups()
112 err = phy_write(phydev,30, temp); in mpc8568_mds_phy_fixups()
117 err = phy_write(phydev,29, 0x000a); in mpc8568_mds_phy_fixups()
134 err = phy_write(phydev,30,temp); in mpc8568_mds_phy_fixups()
146 err = phy_write(phydev,16,temp); in mpc8568_mds_phy_fixups()
/linux/arch/arm/mach-imx/
A Dmach-imx7d.c20 phy_write(dev, 0x1e, 0x21); in bcm54220_phy_fixup()
21 phy_write(dev, 0x1f, 0x7ea8); in bcm54220_phy_fixup()
22 phy_write(dev, 0x1e, 0x2f); in bcm54220_phy_fixup()
23 phy_write(dev, 0x1f, 0x71b7); in bcm54220_phy_fixup()
A Dmach-imx6q.c28 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
30 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); in ksz9021rn_phy_fixup()
33 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
35 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); in ksz9021rn_phy_fixup()
36 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()

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