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Searched refs:phys_enc (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_encoder_phys_cmd.c89 phys_enc->parent_ops->handle_frame_done(phys_enc->parent, in dpu_encoder_phys_cmd_pp_tx_done_irq()
117 phys_enc->parent_ops->handle_vblank_virt(phys_enc->parent, in dpu_encoder_phys_cmd_pp_rd_ptr_irq()
118 phys_enc); in dpu_encoder_phys_cmd_pp_rd_ptr_irq()
143 phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent, in dpu_encoder_phys_cmd_underrun_irq()
144 phys_enc); in dpu_encoder_phys_cmd_underrun_irq()
397 phys_enc->hw_pp->ops.setup_tearcheck(phys_enc->hw_pp, &tc_cfg); in dpu_encoder_phys_cmd_tearcheck_config()
440 dpu_encoder_helper_split_config(phys_enc, phys_enc->intf_idx); in dpu_encoder_phys_cmd_enable_helper()
525 phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, false); in dpu_encoder_phys_cmd_disable()
582 if (!phys_enc) in dpu_encoder_phys_cmd_is_ongoing_pptx()
585 phys_enc->hw_pp->ops.get_vsync_info(phys_enc->hw_pp, &info); in dpu_encoder_phys_cmd_is_ongoing_pptx()
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A Ddpu_encoder_phys_vid.c291 phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, in dpu_encoder_phys_vid_setup_timing_engine()
322 phys_enc->parent_ops->handle_vblank_virt(phys_enc->parent, in dpu_encoder_phys_vid_vblank_irq()
323 phys_enc); in dpu_encoder_phys_vid_vblank_irq()
343 phys_enc->parent_ops->handle_frame_done(phys_enc->parent, phys_enc, in dpu_encoder_phys_vid_vblank_irq()
355 phys_enc); in dpu_encoder_phys_vid_underrun_irq()
551 if (!phys_enc->parent || !phys_enc->parent->dev) { in dpu_encoder_phys_vid_disable()
558 phys_enc->hw_intf != NULL, phys_enc->hw_ctl != NULL); in dpu_encoder_phys_vid_disable()
571 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0); in dpu_encoder_phys_vid_disable()
663 phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &s); in dpu_encoder_phys_vid_get_frame_count()
708 phys_enc = kzalloc(sizeof(*phys_enc), GFP_KERNEL); in dpu_encoder_phys_vid_init()
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A Ddpu_encoder_phys.h135 int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
136 int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
137 int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc);
138 void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
140 void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
141 bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
143 void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
319 struct dpu_encoder_phys *phys_enc) in dpu_encoder_helper_get_3d_blend_mode() argument
323 if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING) in dpu_encoder_helper_get_3d_blend_mode()
328 if (phys_enc->split_role == ENC_ROLE_SOLO && in dpu_encoder_helper_get_3d_blend_mode()
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A Ddpu_encoder.c250 DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0, in dpu_encoder_helper_report_irq_timeout()
255 phys_enc->parent, phys_enc, in dpu_encoder_helper_report_irq_timeout()
274 irq = &phys_enc->irq[intr_idx]; in dpu_encoder_helper_wait_for_irq()
299 DRMID(phys_enc->parent), in dpu_encoder_helper_wait_for_irq()
350 DPU_ERROR_PHYS(phys_enc, in dpu_encoder_helper_register_irq()
358 DPU_ERROR_PHYS(phys_enc, in dpu_encoder_helper_register_irq()
487 if (!phys_enc->hw_mdptop || !phys_enc->parent) { in dpu_encoder_helper_split_config()
516 phys_enc->ops.needs_single_flush(phys_enc)) in dpu_encoder_helper_split_config()
1494 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_trigger_start()
1534 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_hw_reset()
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