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Searched refs:pipe_bpp (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
A Dintel_dp.c606 u32 pipe_bpp) in intel_dp_dsc_get_output_bpp() argument
925 pipe_bpp) >> 4; in intel_dp_mode_valid()
1332 int pipe_bpp; in intel_dp_dsc_compute_config() local
1344 if (pipe_bpp < 8 * 3) { in intel_dp_dsc_compute_config()
1355 pipe_config->pipe_bpp = pipe_bpp; in intel_dp_dsc_compute_config()
1377 pipe_bpp); in intel_dp_dsc_compute_config()
1431 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
1439 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
1521 pipe_config->pipe_bpp, in intel_dp_compute_link_config()
1533 pipe_config->pipe_bpp); in intel_dp_compute_link_config()
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A Dg4x_hdmi.c40 if (crtc_state->pipe_bpp > 24) in intel_hdmi_prepare()
213 if (pipe_config->pipe_bpp > 24 && in ibx_enable_hdmi()
261 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
272 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
A Dintel_lvds.c292 if (pipe_config->dither && pipe_config->pipe_bpp == 18) in intel_pre_enable_lvds()
434 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { in intel_lvds_compute_config()
437 pipe_config->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
438 pipe_config->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
A Dintel_fdi.c247 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
251 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, in ilk_fdi_compute_config()
258 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { in ilk_fdi_compute_config()
259 pipe_config->pipe_bpp -= 2*3; in ilk_fdi_compute_config()
262 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
A Dintel_dp_mst.c67 crtc_state->pipe_bpp = bpp; in intel_dp_mst_compute_link_config()
70 crtc_state->pipe_bpp, in intel_dp_mst_compute_link_config()
91 intel_link_compute_m_n(crtc_state->pipe_bpp, in intel_dp_mst_compute_link_config()
149 limits.max_bpp = min(pipe_config->pipe_bpp, 24); in intel_dp_mst_compute_config()
A Dintel_hdmi.c933 static bool gcp_default_phase_possible(int pipe_bpp, in gcp_default_phase_possible() argument
938 switch (pipe_bpp) { in gcp_default_phase_possible()
1028 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
1032 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_compute_gcp_infoframe()
1996 if (crtc_state->pipe_bpp < bpc * 3) in intel_hdmi_deep_color_possible()
2081 if (crtc_state->pipe_bpp > bpc * 3) in intel_hdmi_compute_clock()
2082 crtc_state->pipe_bpp = bpc * 3; in intel_hdmi_compute_clock()
2086 bpc, crtc_state->pipe_bpp); in intel_hdmi_compute_clock()
A Dintel_ddi.c331 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; in ddi_dotclock_get()
360 switch (crtc_state->pipe_bpp) { in intel_ddi_set_dp_msa()
374 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_dp_msa()
451 switch (crtc_state->pipe_bpp) { in intel_ddi_transcoder_func_reg_val_get()
3457 pipe_config->pipe_bpp = 18; in intel_ddi_read_func_ctl()
3460 pipe_config->pipe_bpp = 24; in intel_ddi_read_func_ctl()
3463 pipe_config->pipe_bpp = 30; in intel_ddi_read_func_ctl()
3466 pipe_config->pipe_bpp = 36; in intel_ddi_read_func_ctl()
3574 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { in intel_ddi_get_config()
3590 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); in intel_ddi_get_config()
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A Dg4x_dp.c400 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { in intel_dp_get_config()
416 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); in intel_dp_get_config()
417 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; in intel_dp_get_config()
A Dintel_display.c3405 if (crtc_state->pipe_bpp > 24) in hsw_crtc_state_ips_capable()
4215 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
4218 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
4221 pipe_config->pipe_bpp = 30; in i9xx_get_pipe_config()
5082 pipe_config->pipe_bpp = 18; in ilk_get_pipe_config()
5085 pipe_config->pipe_bpp = 24; in ilk_get_pipe_config()
5088 pipe_config->pipe_bpp = 30; in ilk_get_pipe_config()
5091 pipe_config->pipe_bpp = 36; in ilk_get_pipe_config()
6515 pipe_config->pipe_bpp); in compute_sink_pipe_bpp()
6517 pipe_config->pipe_bpp = bpp; in compute_sink_pipe_bpp()
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A Dicl_dsi.c1569 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in gen11_dsi_get_config()
1614 if (crtc_state->pipe_bpp < 8 * 3) in gen11_dsi_dsc_compute_config()
1679 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1681 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
A Dintel_crt.c436 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { in hsw_crt_compute_config()
442 pipe_config->pipe_bpp = 24; in hsw_crt_compute_config()
A Dvlv_dsi.c295 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
297 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
1127 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in bxt_dsi_get_pipe_config()
A Dintel_panel.c474 if (DISPLAY_VER(dev_priv) < 4 && crtc_state->pipe_bpp == 18) in gmch_panel_fitting()
A Dintel_audio.c276 if (crtc_state->pipe_bpp == 36) { in audio_config_hdmi_get_n()
279 } else if (crtc_state->pipe_bpp == 30) { in audio_config_hdmi_get_n()
A Dintel_psr.c881 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
884 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
A Dintel_vdsc.c467 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
A Dintel_bios.c2775 crtc_state->pipe_bpp = bpc * 3; in fill_dsc()
2777 crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, in fill_dsc()
A Dintel_display_types.h1059 int pipe_bpp; member
A Dintel_tv.c1205 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
A Dintel_display_debugfs.c1030 yesno(crtc_state->dither), crtc_state->pipe_bpp); in intel_crtc_info()
A Dintel_sdvo.c1316 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()

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