| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hw_sequencer_debug.c | 133 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_hubp_states()
203 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_rq_states()
248 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_dlg_states()
302 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_ttu_states()
341 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_cm_states()
394 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_mpcc_states()
509 for (i = 0; i < pool->pipe_count; i++) { in dcn10_clear_hubp_underflow()
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| A D | dcn10_hw_sequencer.c | 101 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
171 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
203 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
228 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
260 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
293 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
335 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
1023 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn10_reset_back_end_for_pipe()
1027 if (i == dc->res_pool->pipe_count) in dcn10_reset_back_end_for_pipe()
3154 for (i = 0; i < res_pool->pipe_count; i++) { in get_hubp_by_inst()
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| A D | dcn10_resource.c | 986 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_destruct()
1410 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1413 pool->base.pipe_count = 3; in dcn10_resource_construct()
1569 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_construct()
1638 pool->base.pipe_count = j; in dcn10_resource_construct()
1644 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1645 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1667 dc->caps.max_planes = pool->base.pipe_count; in dcn10_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| A D | dce60_resource.c | 800 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_resource_destruct()
873 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_validate_bandwidth()
959 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
1034 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_construct()
1096 dc->caps.max_planes = pool->base.pipe_count; in dce60_construct()
1153 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1231 for (i = 0; i < pool->base.pipe_count; i++) { in dce61_construct()
1293 dc->caps.max_planes = pool->base.pipe_count; in dce61_construct()
1350 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1424 for (i = 0; i < pool->base.pipe_count; i++) { in dce64_construct()
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| A D | dce60_hw_sequencer.c | 70 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_should_enable_fbc()
86 if (i == dc->res_pool->pipe_count) in dce60_should_enable_fbc()
395 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_apply_ctx_for_surface()
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| /linux/drivers/gpu/drm/amd/display/dc/dce80/ |
| A D | dce80_resource.c | 805 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_resource_destruct()
878 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce80_validate_bandwidth()
964 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
1045 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
1107 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1164 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1244 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1306 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1363 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1439 for (i = 0; i < pool->base.pipe_count; i++) { in dce83_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| A D | dce110_resource.c | 816 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_destruct()
979 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
1267 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1268 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; in underlay_create()
1269 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1270 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; in underlay_create()
1271 pool->pipe_count++; in underlay_create()
1365 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1366 pool->base.underlay_pipe_index = pool->base.pipe_count; in dce110_resource_construct()
1440 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_resource.c | 1487 for (i = 0; i < pool->base.pipe_count; i++) { in dcn20_resource_destruct()
3401 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create() local
3403 for (i = 0; i < pipe_count; i++) { in dcn20_dwbc_create()
3424 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create() local
3426 ASSERT(pipe_count > 0); in dcn20_mmhubbub_create()
3428 for (i = 0; i < pipe_count; i++) { in dcn20_mmhubbub_create()
3738 pool->base.pipe_count = 5; in dcn20_resource_construct()
3742 pool->base.pipe_count = 6; in dcn20_resource_construct()
3802 pool->base.pipe_count = 4; in dcn20_resource_construct()
3944 for (i = 0; i < pool->base.pipe_count; i++) { in dcn20_resource_construct()
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| A D | dcn20_hwseq.c | 1469 int opp_count = dc->res_pool->pipe_count; in dcn20_update_dchubp_dpp()
1688 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1693 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1702 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1717 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1751 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_post_unlock_program_front_end()
1761 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_post_unlock_program_front_end()
1774 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_post_unlock_program_front_end()
1786 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_post_unlock_program_front_end()
2236 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_reset_back_end_for_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc.c | 1084 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
1131 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vbios_mode_if_required()
1227 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
1319 int pipe_count = dc->res_pool->pipe_count; in enable_timing_multisync() local
1322 for (i = 0; i < pipe_count; i++) { in enable_timing_multisync()
1345 int pipe_count = dc->res_pool->pipe_count; in program_timing_sync() local
1348 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1355 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1369 for (j = i + 1; j < pipe_count; j++) { in program_timing_sync()
1657 for (i = 0; i < dc->res_pool->pipe_count; i++) { in get_stream_mask()
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| A D | dc_surface.c | 150 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
162 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
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| A D | dc_debug.c | 318 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
330 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_resource.c | 1241 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1322 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1359 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create() local
1361 for (i = 0; i < pipe_count; i++) { in dcn30_dwbc_create()
1384 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create() local
1386 for (i = 0; i < pipe_count; i++) { in dcn30_mmhubbub_create()
1605 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1734 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
1951 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_internal_validate_bw()
2755 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn302/ |
| A D | dcn302_resource.c | 845 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create() local
847 for (i = 0; i < pipe_count; i++) { in dcn302_dwbc_create()
880 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create() local
882 for (i = 0; i < pipe_count; i++) { in dcn302_mmhubbub_create()
1105 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
1106 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
1166 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1241 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1506 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
1640 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn303/ |
| A D | dcn303_resource.c | 787 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create() local
789 for (i = 0; i < pipe_count; i++) { in dcn303_dwbc_create()
822 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create() local
824 for (i = 0; i < pipe_count; i++) { in dcn303_mmhubbub_create()
1031 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
1032 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
1092 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1167 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1446 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
1571 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| A D | dcn301_resource.c | 1095 for (i = 0; i < pool->base.pipe_count; i++) { in dcn301_destruct()
1207 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create() local
1209 for (i = 0; i < pipe_count; i++) { in dcn301_dwbc_create()
1232 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create() local
1234 for (i = 0; i < pipe_count; i++) { in dcn301_mmhubbub_create()
1331 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
1437 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn301_resource_construct()
1578 for (i = 0; i < pool->base.pipe_count; i++) { in dcn301_resource_construct()
1621 pool->base.pipe_count = j; in dcn301_resource_construct()
1696 dc->caps.max_planes = pool->base.pipe_count; in dcn301_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_resource.c | 943 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_destruct()
1113 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_calculate_wm()
1235 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
1259 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
1343 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dcn21_validate_bandwidth_fp()
1599 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; in update_bw_bounding_box()
1978 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
2034 pool->base.pipe_count = 4; in dcn21_resource_construct()
2145 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_construct()
2213 pool->base.pipe_count = j; in dcn21_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dce100/ |
| A D | dce100_resource.c | 757 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_destruct()
844 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce100_validate_bandwidth()
1065 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1076 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_construct()
1139 dc->caps.max_planes = pool->base.pipe_count; in dce100_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_resource.c | 1563 for (i = 0; i < pool->base.pipe_count; i++) { in dcn31_resource_destruct()
1678 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1680 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1703 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1705 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1788 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_populate_dml_pipes_from_context()
1967 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
2068 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn31_update_bw_bounding_box()
2195 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn31_resource_construct()
2352 for (i = 0; i < pool->base.pipe_count; i++) { in dcn31_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dce120/ |
| A D | dce120_resource.c | 600 for (i = 0; i < pool->base.pipe_count; i++) { in dce120_resource_destruct()
1070 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1159 for (i = 0; i < pool->base.pipe_count; i++) { in dce120_resource_construct()
1235 pool->base.pipe_count = j; in dce120_resource_construct()
1250 dc->caps.max_planes = pool->base.pipe_count; in dce120_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 72 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
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| /linux/sound/pci/mixart/ |
| A D | mixart_core.h | 232 u32 pipe_count; /* set to 1 for instance */ member
394 u32 pipe_count; /* set to 1 (array size !) */ member
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_resource.c | 937 for (i = 0; i < pool->base.pipe_count; i++) { in dcn201_resource_destruct()
1096 pool->base.pipe_count = 4; in dcn201_resource_construct()
1187 dcn201_ip.max_num_dpp = pool->base.pipe_count; in dcn201_resource_construct()
1198 for (i = 0; i < pool->base.pipe_count; i++) { in dcn201_resource_construct()
1276 dc->caps.max_planes = pool->base.pipe_count; in dcn201_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dce112/ |
| A D | dce112_resource.c | 778 for (i = 0; i < pool->base.pipe_count; i++) { in dce112_resource_destruct()
901 dc->res_pool->pipe_count, in dce112_validate_bandwidth()
1234 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1321 for (i = 0; i < pool->base.pipe_count; i++) { in dce112_resource_construct()
1390 dc->caps.max_planes = pool->base.pipe_count; in dce112_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| A D | dcn20_clk_mgr.c | 111 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
145 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
176 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
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