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Searched refs:queue_mask (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/soc/ti/
A Dknav_qmss_acc.c283 cmd->command, cmd->queue_mask, cmd->list_dma, in knav_acc_write()
289 writel_relaxed(cmd->queue_mask, &pdsp->acc_command->queue_mask); in knav_acc_write()
308 u32 queue_mask; in knav_acc_setup_cmd() local
313 queue_mask = BIT(range->num_queues) - 1; in knav_acc_setup_cmd()
317 queue_mask = 0; in knav_acc_setup_cmd()
322 cmd->queue_mask = queue_mask; in knav_acc_setup_cmd()
A Dknav_qmss.h89 u32 queue_mask; member
/linux/drivers/gpu/drm/amd/amdkfd/
A Dkfd_packet_manager_vi.c135 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_vi()
136 packet->queue_mask_hi = upper_32_bits(res->queue_mask); in pm_set_resources_vi()
A Dkfd_packet_manager_v9.c175 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_v9()
176 packet->queue_mask_hi = upper_32_bits(res->queue_mask); in pm_set_resources_v9()
A Dkfd_device_queue_manager.c1112 res.queue_mask = 0; in set_sched_resources()
1128 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) { in set_sched_resources()
1133 res.queue_mask |= 1ull in set_sched_resources()
1143 res.vmid_mask, res.queue_mask); in set_sched_resources()
A Dkfd_priv.h568 uint64_t queue_mask; member
/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_gfx.c505 uint64_t queue_mask = 0; in amdgpu_gfx_enable_kcq() local
518 if (WARN_ON(i > (sizeof(queue_mask)*8))) { in amdgpu_gfx_enable_kcq()
523 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i)); in amdgpu_gfx_enable_kcq()
538 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask); in amdgpu_gfx_enable_kcq()
A Damdgpu_gfx.h83 uint64_t queue_mask);
A Dgfx_v8_0.c4361 uint64_t queue_mask = 0; in gfx_v8_0_kiq_kcq_enable() local
4371 if (WARN_ON(i >= (sizeof(queue_mask)*8))) { in gfx_v8_0_kiq_kcq_enable()
4376 queue_mask |= (1ull << i); in gfx_v8_0_kiq_kcq_enable()
4387 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v8_0_kiq_kcq_enable()
4388 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v8_0_kiq_kcq_enable()
A Dgfx_v9_0.c832 uint64_t queue_mask) in gfx_v9_0_kiq_set_resources() argument
840 lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v9_0_kiq_set_resources()
842 upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v9_0_kiq_set_resources()
A Dgfx_v10_0.c3591 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) in gfx10_kiq_set_resources() argument
3596 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx10_kiq_set_resources()
3597 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx10_kiq_set_resources()
/linux/drivers/net/ethernet/marvell/
A Dmv643xx_eth.c2254 u8 queue_mask; in mv643xx_eth_poll() local
2265 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx; in mv643xx_eth_poll()
2267 queue_mask |= mp->work_rx_refill; in mv643xx_eth_poll()
2269 if (!queue_mask) { in mv643xx_eth_poll()
2275 queue = fls(queue_mask) - 1; in mv643xx_eth_poll()
2276 queue_mask = 1 << queue; in mv643xx_eth_poll()
2282 if (mp->work_tx_end & queue_mask) { in mv643xx_eth_poll()
2284 } else if (mp->work_tx & queue_mask) { in mv643xx_eth_poll()
2287 } else if (mp->work_rx & queue_mask) { in mv643xx_eth_poll()
2289 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) { in mv643xx_eth_poll()
/linux/net/ethtool/
A Dioctl.c2477 DECLARE_BITMAP(queue_mask, MAX_NUM_QUEUE); in ethtool_get_per_queue_coalesce()
2484 bitmap_from_arr32(queue_mask, per_queue_opt->queue_mask, in ethtool_get_per_queue_coalesce()
2487 for_each_set_bit(bit, queue_mask, MAX_NUM_QUEUE) { in ethtool_get_per_queue_coalesce()
2510 DECLARE_BITMAP(queue_mask, MAX_NUM_QUEUE); in ethtool_set_per_queue_coalesce()
2518 bitmap_from_arr32(queue_mask, per_queue_opt->queue_mask, MAX_NUM_QUEUE); in ethtool_set_per_queue_coalesce()
2519 n_queue = bitmap_weight(queue_mask, MAX_NUM_QUEUE); in ethtool_set_per_queue_coalesce()
2524 for_each_set_bit(bit, queue_mask, MAX_NUM_QUEUE) { in ethtool_set_per_queue_coalesce()
2553 for_each_set_bit(i, queue_mask, bit) { in ethtool_set_per_queue_coalesce()
/linux/drivers/net/ethernet/cadence/
A Dmacb_main.c3729 unsigned int *queue_mask, in macb_probe_queues() argument
3732 *queue_mask = 0x1; in macb_probe_queues()
3745 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff; in macb_probe_queues()
3746 *num_queues = hweight32(*queue_mask); in macb_probe_queues()
3865 if (!(bp->queue_mask & (1 << hw_q))) in macb_init()
4668 unsigned int queue_mask, num_queues; in macb_probe() local
4703 macb_probe_queues(mem, native_io, &queue_mask, &num_queues); in macb_probe()
4727 bp->queue_mask = queue_mask; in macb_probe()
A Dmacb.h1253 unsigned int queue_mask; member
/linux/net/sched/
A Dsch_taprio.c1208 u32 i, queue_mask = 0; in tc_map_to_queue_mask() local
1219 queue_mask |= GENMASK(offset + count - 1, offset); in tc_map_to_queue_mask()
1222 return queue_mask; in tc_map_to_queue_mask()
/linux/include/uapi/linux/
A Dethtool.h1422 __u32 queue_mask[__KERNEL_DIV_ROUND_UP(MAX_NUM_QUEUE, 32)]; member
/linux/Documentation/networking/device_drivers/ethernet/intel/
A Dice.rst968 # ethtool --per-queue <ethX> queue_mask 0xa --coalesce adaptive-rx off
973 # ethtool --per-queue <ethX> queue_mask 0xa --show-coalesce

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