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Searched refs:reg_num (Results 1 – 25 of 139) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/
A Dirq_service_dcn201.c174 #define hpd_int_entry(reg_num)\ argument
176 IRQ_REG_ENTRY(HPD, reg_num,\
183 #define hpd_rx_int_entry(reg_num)\ argument
185 IRQ_REG_ENTRY(HPD, reg_num,\
191 #define pflip_int_entry(reg_num)\ argument
193 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
201 IRQ_REG_ENTRY(OTG, reg_num,\
212 IRQ_REG_ENTRY(OTG, reg_num,\
219 IRQ_REG_ENTRY(OTG, reg_num,\
227 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/irq/dce120/
A Dirq_service_dce120.c119 #define hpd_int_entry(reg_num)\ argument
121 IRQ_REG_ENTRY(HPD, reg_num,\
128 #define hpd_rx_int_entry(reg_num)\ argument
130 IRQ_REG_ENTRY(HPD, reg_num,\
136 #define pflip_int_entry(reg_num)\ argument
138 IRQ_REG_ENTRY(DCP, reg_num, \
145 #define vupdate_int_entry(reg_num)\ argument
147 IRQ_REG_ENTRY(CRTC, reg_num,\
153 #define vblank_int_entry(reg_num)\ argument
155 IRQ_REG_ENTRY(CRTC, reg_num,\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/irq/dce80/
A Dirq_service_dce80.c94 #define hpd_int_entry(reg_num)\ argument
95 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
109 #define hpd_rx_int_entry(reg_num)\ argument
110 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
123 #define pflip_int_entry(reg_num)\ argument
124 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
138 #define vupdate_int_entry(reg_num)\ argument
154 #define vblank_int_entry(reg_num)\ argument
176 #define i2c_int_entry(reg_num) \ argument
179 #define dp_sink_int_entry(reg_num) \ argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/
A Dirq_service_dcn303.c123 #define hpd_int_entry(reg_num)\ argument
125 IRQ_REG_ENTRY(HPD, reg_num,\
132 #define hpd_rx_int_entry(reg_num)\ argument
134 IRQ_REG_ENTRY(HPD, reg_num,\
140 #define pflip_int_entry(reg_num)\ argument
142 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
153 IRQ_REG_ENTRY(OTG, reg_num,\
159 #define vblank_int_entry(reg_num)\ argument
161 IRQ_REG_ENTRY(OTG, reg_num,\
169 #define i2c_int_entry(reg_num) \ argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn10/
A Dirq_service_dcn10.c217 #define hpd_int_entry(reg_num)\ argument
219 IRQ_REG_ENTRY(HPD, reg_num,\
226 #define hpd_rx_int_entry(reg_num)\ argument
228 IRQ_REG_ENTRY(HPD, reg_num,\
234 #define pflip_int_entry(reg_num)\ argument
236 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
247 IRQ_REG_ENTRY(OTG, reg_num,\
253 #define vblank_int_entry(reg_num)\ argument
255 IRQ_REG_ENTRY(OTG, reg_num,\
263 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn20/
A Dirq_service_dcn20.c246 #define hpd_int_entry(reg_num)\ argument
248 IRQ_REG_ENTRY(HPD, reg_num,\
255 #define hpd_rx_int_entry(reg_num)\ argument
257 IRQ_REG_ENTRY(HPD, reg_num,\
263 #define pflip_int_entry(reg_num)\ argument
265 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
276 IRQ_REG_ENTRY(OTG, reg_num,\
282 #define vblank_int_entry(reg_num)\ argument
284 IRQ_REG_ENTRY(OTG, reg_num,\
292 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/irq/dce60/
A Dirq_service_dce60.c101 #define hpd_int_entry(reg_num)\ argument
102 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
116 #define hpd_rx_int_entry(reg_num)\ argument
117 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
130 #define pflip_int_entry(reg_num)\ argument
131 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
145 #define vupdate_int_entry(reg_num)\ argument
161 #define vblank_int_entry(reg_num)\ argument
182 #define i2c_int_entry(reg_num) \ argument
185 #define dp_sink_int_entry(reg_num) \ argument
[all …]
/linux/arch/sparc/kernel/
A Dpcr.c59 WARN_ON_ONCE(reg_num != 0); in direct_pcr_read()
66 WARN_ON_ONCE(reg_num != 0); in direct_pcr_write()
74 WARN_ON_ONCE(reg_num != 0); in direct_pic_read()
81 WARN_ON_ONCE(reg_num != 0); in direct_pic_write()
115 WARN_ON_ONCE(reg_num != 0); in n2_pcr_write()
119 direct_pcr_write(reg_num, val); in n2_pcr_write()
121 direct_pcr_write(reg_num, val); in n2_pcr_write()
148 (void) sun4v_vt_get_perfreg(reg_num, &val); in n4_pcr_read()
155 (void) sun4v_vt_set_perfreg(reg_num, val); in n4_pcr_write()
206 (void) sun4v_t5_set_perfreg(reg_num, val); in n5_pcr_write()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/
A Dirq_service_dcn21.c269 #define hpd_int_entry(reg_num)\ argument
271 IRQ_REG_ENTRY(HPD, reg_num,\
278 #define hpd_rx_int_entry(reg_num)\ argument
280 IRQ_REG_ENTRY(HPD, reg_num,\
286 #define pflip_int_entry(reg_num)\ argument
288 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
296 IRQ_REG_ENTRY(OTG, reg_num,\
307 IRQ_REG_ENTRY(OTG, reg_num,\
315 IRQ_REG_ENTRY(OTG, reg_num,\
323 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/
A Dirq_service_dcn30.c250 #define hpd_int_entry(reg_num)\ argument
252 IRQ_REG_ENTRY(HPD, reg_num,\
259 #define hpd_rx_int_entry(reg_num)\ argument
261 IRQ_REG_ENTRY(HPD, reg_num,\
267 #define pflip_int_entry(reg_num)\ argument
269 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
280 IRQ_REG_ENTRY(OTG, reg_num,\
286 #define vblank_int_entry(reg_num)\ argument
288 IRQ_REG_ENTRY(OTG, reg_num,\
296 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/
A Dirq_service_dcn302.c227 #define hpd_int_entry(reg_num)\ argument
229 IRQ_REG_ENTRY(HPD, reg_num,\
236 #define hpd_rx_int_entry(reg_num)\ argument
238 IRQ_REG_ENTRY(HPD, reg_num,\
244 #define pflip_int_entry(reg_num)\ argument
257 IRQ_REG_ENTRY(OTG, reg_num,\
263 #define vblank_int_entry(reg_num)\ argument
265 IRQ_REG_ENTRY(OTG, reg_num,\
271 #define vline0_int_entry(reg_num)\ argument
273 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/
A Dirq_service_dcn31.c237 #define hpd_int_entry(reg_num)\ argument
239 IRQ_REG_ENTRY(HPD, reg_num,\
246 #define hpd_rx_int_entry(reg_num)\ argument
248 IRQ_REG_ENTRY(HPD, reg_num,\
254 #define pflip_int_entry(reg_num)\ argument
256 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
267 IRQ_REG_ENTRY(OTG, reg_num,\
273 #define vblank_int_entry(reg_num)\ argument
275 IRQ_REG_ENTRY(OTG, reg_num,\
283 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/irq/dce110/
A Dirq_service_dce110.c91 #define hpd_int_entry(reg_num)\ argument
92 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
106 #define hpd_rx_int_entry(reg_num)\ argument
107 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
119 #define pflip_int_entry(reg_num)\ argument
120 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
134 #define vupdate_int_entry(reg_num)\ argument
150 #define vblank_int_entry(reg_num)\ argument
172 #define i2c_int_entry(reg_num) \ argument
175 #define dp_sink_int_entry(reg_num) \ argument
[all …]
/linux/arch/riscv/kvm/
A Dvcpu_fp.c94 if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr)) in kvm_riscv_vcpu_get_reg_fp()
97 reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) in kvm_riscv_vcpu_get_reg_fp()
98 reg_val = &cntx->fp.f.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp()
103 if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { in kvm_riscv_vcpu_get_reg_fp()
108 reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) { in kvm_riscv_vcpu_get_reg_fp()
111 reg_val = &cntx->fp.d.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp()
140 if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr)) in kvm_riscv_vcpu_set_reg_fp()
143 reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) in kvm_riscv_vcpu_set_reg_fp()
144 reg_val = &cntx->fp.f.f[reg_num]; in kvm_riscv_vcpu_set_reg_fp()
149 if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { in kvm_riscv_vcpu_set_reg_fp()
[all …]
A Dvcpu.c161 switch (reg_num) { in kvm_riscv_vcpu_get_reg_config()
191 switch (reg_num) { in kvm_riscv_vcpu_set_reg_config()
228 reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6)) in kvm_riscv_vcpu_get_reg_core()
229 reg_val = ((unsigned long *)cntx)[reg_num]; in kvm_riscv_vcpu_get_reg_core()
264 reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6)) in kvm_riscv_vcpu_set_reg_core()
265 ((unsigned long *)cntx)[reg_num] = reg_val; in kvm_riscv_vcpu_set_reg_core()
293 if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) { in kvm_riscv_vcpu_get_reg_csr()
297 reg_val = ((unsigned long *)csr)[reg_num]; in kvm_riscv_vcpu_get_reg_csr()
324 if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) { in kvm_riscv_vcpu_set_reg_csr()
329 ((unsigned long *)csr)[reg_num] = reg_val; in kvm_riscv_vcpu_set_reg_csr()
[all …]
A Dvcpu_timer.c97 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_timer() local
104 if (reg_num >= sizeof(struct kvm_riscv_timer) / sizeof(u64)) in kvm_riscv_vcpu_get_reg_timer()
107 switch (reg_num) { in kvm_riscv_vcpu_get_reg_timer()
137 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_timer() local
145 if (reg_num >= sizeof(struct kvm_riscv_timer) / sizeof(u64)) in kvm_riscv_vcpu_set_reg_timer()
151 switch (reg_num) { in kvm_riscv_vcpu_set_reg_timer()
/linux/drivers/video/fbdev/via/
A Dhw.h355 int reg_num; member
361 int reg_num; member
367 int reg_num; member
373 int reg_num; member
379 int reg_num; member
385 int reg_num; member
391 int reg_num; member
397 int reg_num; member
403 int reg_num; member
409 int reg_num; member
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/linux/drivers/irqchip/
A Dirq-imx-irqsteer.c33 int reg_num; member
42 return (data->reg_num - irqnum / 32 - 1); in imx_irqsteer_get_reg_index()
53 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask()
127 if (hwirq >= data->reg_num * 32) in imx_irqsteer_irq_handler()
131 CHANSTATUS(idx, data->reg_num)); in imx_irqsteer_irq_handler()
176 data->reg_num = irqs_num / 32; in imx_irqsteer_probe()
180 sizeof(u32) * data->reg_num, in imx_irqsteer_probe()
249 for (i = 0; i < data->reg_num; i++) in imx_irqsteer_save_regs()
251 CHANMASK(i, data->reg_num)); in imx_irqsteer_save_regs()
259 for (i = 0; i < data->reg_num; i++) in imx_irqsteer_restore_regs()
[all …]
/linux/arch/powerpc/platforms/powernv/
A Dopal-fadump.h82 __be32 reg_num; member
87 u32 reg_type, u32 reg_num, in opal_fadump_set_regval_regnum() argument
91 if (reg_num < 32) in opal_fadump_set_regval_regnum()
92 regs->gpr[reg_num] = reg_val; in opal_fadump_set_regval_regnum()
96 switch (reg_num) { in opal_fadump_set_regval_regnum()
141 be32_to_cpu(reg_entry->reg_num), in opal_fadump_read_regs()
/linux/drivers/net/ethernet/arc/
A Demac_mdio.c56 static int arc_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num) in arc_mdio_read() argument
63 0x60020000 | (phy_addr << 23) | (reg_num << 18)); in arc_mdio_read()
72 phy_addr, reg_num, value); in arc_mdio_read()
89 int reg_num, u16 value) in arc_mdio_write() argument
95 phy_addr, reg_num, value); in arc_mdio_write()
98 0x50020000 | (phy_addr << 23) | (reg_num << 18) | value); in arc_mdio_write()
/linux/drivers/input/keyboard/
A Dbcm-keypad.c103 static void bcm_kp_report_keys(struct bcm_kp *kp, int reg_num, int pull_mode) in bcm_kp_report_keys() argument
112 writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num)); in bcm_kp_report_keys()
114 state = readl(kp->base + KPSSRN_OFFSET(reg_num)); in bcm_kp_report_keys()
115 change = kp->last_state[reg_num] ^ state; in bcm_kp_report_keys()
116 kp->last_state[reg_num] = state; in bcm_kp_report_keys()
122 row = BIT_TO_ROW_SSRN(bit_nr, reg_num); in bcm_kp_report_keys()
133 int reg_num; in bcm_kp_isr_thread() local
135 for (reg_num = 0; reg_num <= 1; reg_num++) in bcm_kp_isr_thread()
136 bcm_kp_report_keys(kp, reg_num, pull_mode); in bcm_kp_isr_thread()
/linux/drivers/crypto/qat/qat_common/
A Dqat_hal.c248 unsigned short reg_num) in qat_hal_get_reg_addr() argument
255 reg_addr = 0x80 | (reg_num & 0x7f); in qat_hal_get_reg_addr()
259 reg_addr = reg_num & 0x1f; in qat_hal_get_reg_addr()
264 reg_addr = 0x180 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
272 reg_addr = 0x1c0 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
1364 if (reg_num & ~mask) in qat_hal_put_rel_rd_xfer()
1366 reg_addr = reg_num + (ctx << 0x5); in qat_hal_put_rel_rd_xfer()
1413 if (reg_num & reg_mask) in qat_hal_put_rel_wr_xfer()
1500 reg = reg_num; in qat_hal_init_gpr()
1534 reg = reg_num; in qat_hal_init_wr_xfer()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
A Ddm_services.h164 #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\ argument
167 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
168 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
170 #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\ argument
174 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
175 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
/linux/drivers/w1/
A Dw1.c102 ssize_t count = sizeof(sl->reg_num); in id_show()
104 memcpy(buf, (u8 *)&sl->reg_num, count); in id_show()
449 sl->reg_num.id == rn->id && in w1_slave_search_device()
450 sl->reg_num.crc == rn->crc) { in w1_slave_search_device()
687 (unsigned int) sl->reg_num.family, in __w1_attach_slave_device()
688 (unsigned long long) sl->reg_num.id); in __w1_attach_slave_device()
691 (unsigned int) sl->reg_num.family, in __w1_attach_slave_device()
741 memcpy(&sl->reg_num, rn, sizeof(sl->reg_num)); in w1_attach_slave_device()
860 sl->reg_num.id == id->id && in w1_search_slave()
861 sl->reg_num.crc == id->crc) { in w1_search_slave()
[all …]
/linux/drivers/soc/fsl/qe/
A Ducc.c89 unsigned int *reg_num, unsigned int *shift) in get_cmxucr_reg() argument
93 *reg_num = cmx + 1; in get_cmxucr_reg()
101 unsigned int reg_num; in ucc_mux_set_grant_tsa_bkpt() local
108 get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift); in ucc_mux_set_grant_tsa_bkpt()
122 unsigned int reg_num; in ucc_set_qe_mux_rxtx() local
134 get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift); in ucc_set_qe_mux_rxtx()
136 switch (reg_num) { in ucc_set_qe_mux_rxtx()

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