Searched refs:region_base (Results 1 – 6 of 6) sorted by relevance
262 u64 bar_phys_base, region_base, region_end_address; in hl_pci_set_inbound_region() local271 region_base = bar_phys_base + pci_region->offset_in_bar; in hl_pci_set_inbound_region()272 region_end_address = region_base + pci_region->size - 1; in hl_pci_set_inbound_region()275 lower_32_bits(region_base)); in hl_pci_set_inbound_region()277 upper_32_bits(region_base)); in hl_pci_set_inbound_region()380 if ((addr >= region->region_base) && in hl_get_pci_memory_region()381 (addr < region->region_base + region->region_size)) in hl_get_pci_memory_region()
925 unsigned long base_ptr, region_base, region_size; in octeon_prune_device_tree() local952 region_base = mio_boot_reg_cfg.s.base << 16; in octeon_prune_device_tree()954 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base in octeon_prune_device_tree()955 && base_ptr < region_base + region_size) { in octeon_prune_device_tree()1007 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); in octeon_prune_device_tree()1008 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); in octeon_prune_device_tree()1029 unsigned long base_ptr, region_base, region_size; in octeon_prune_device_tree() local1042 region_base = mio_boot_reg_cfg.s.base << 16; in octeon_prune_device_tree()1044 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base in octeon_prune_device_tree()1045 && base_ptr < region_base + region_size) in octeon_prune_device_tree()[all …]
1598 if (end_addr >= region->region_base + region->region_size) { in hl_fw_dynamic_validate_memory_bound()1610 if (end_addr >= region->region_base - region->offset_in_bar + in hl_fw_dynamic_validate_memory_bound()1716 device_addr = region->region_base + response->ram_offset; in hl_fw_dynamic_validate_response()1868 (addr - region->region_base); in hl_fw_dynamic_copy_image()1900 (addr - region->region_base); in hl_fw_dynamic_copy_msg()
954 u64 region_base; member
870 region->region_base = CFG_BASE; in goya_set_pci_memory_regions()879 region->region_base = SRAM_BASE_ADDR; in goya_set_pci_memory_regions()888 region->region_base = DRAM_PHYS_BASE; in goya_set_pci_memory_regions()
1781 region->region_base = CFG_BASE; in gaudi_set_pci_memory_regions()1790 region->region_base = SRAM_BASE_ADDR; in gaudi_set_pci_memory_regions()1799 region->region_base = DRAM_PHYS_BASE; in gaudi_set_pci_memory_regions()1808 region->region_base = PSOC_SCRATCHPAD_ADDR; in gaudi_set_pci_memory_regions()
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